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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2020-12-01 18:13:12 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-12-23 23:04:14 +0300 |
| commit | 554bdbf6de74f5bd5852ce147c06172beb25a831 (patch) | |
| tree | 403701a97a11ba3c16510f547ac61639a7992d56 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 21822b6a968d948ae6cd09dfe7f4e43916d97b0e (diff) | |
| download | linux-554bdbf6de74f5bd5852ce147c06172beb25a831.tar.xz | |
drm/amdgpu: use cached ih rb control reg offsets for vega10
all the ih rb control register offsets are cached
at the beginning of ih_sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions