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authorSteven Eckhoff <steven.eckhoff.opensource@gmail.com>2018-06-04 23:47:02 +0300
committerMark Brown <broonie@kernel.org>2018-06-18 14:54:38 +0300
commit53af408cd9f2d1c66bc081c1d82797bfe44af3e5 (patch)
tree923f4ee81c34f1700e26edfd256509ad0ce3c672 /sound
parent19d996cc3ad698379bcd8482dabe78abe3dc8d96 (diff)
downloadlinux-53af408cd9f2d1c66bc081c1d82797bfe44af3e5.tar.xz
ASoC: TSCS42xx: Add headphone auto switching
Add headphone auto switching controls Signed-off-by: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/tscs42xx.c6
-rw-r--r--sound/soc/codecs/tscs42xx.h8
2 files changed, 14 insertions, 0 deletions
diff --git a/sound/soc/codecs/tscs42xx.c b/sound/soc/codecs/tscs42xx.c
index 5d596e4dab0c..7396a6e5277e 100644
--- a/sound/soc/codecs/tscs42xx.c
+++ b/sound/soc/codecs/tscs42xx.c
@@ -647,6 +647,12 @@ static const struct snd_kcontrol_new tscs42xx_snd_controls[] = {
/* Mic Bias */
SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0),
+ /* Headphone Auto Switching */
+ SOC_SINGLE("Headphone Auto Switching Switch",
+ R_CTL, FB_CTL_HPSWEN, 1, 0),
+ SOC_SINGLE("Headphone Detect Polarity Toggle Switch",
+ R_CTL, FB_CTL_HPSWPOL, 1, 0),
+
/* Coefficient Ram */
COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00),
COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05),
diff --git a/sound/soc/codecs/tscs42xx.h b/sound/soc/codecs/tscs42xx.h
index 814c8f3c4a68..6b3a21081635 100644
--- a/sound/soc/codecs/tscs42xx.h
+++ b/sound/soc/codecs/tscs42xx.h
@@ -34,6 +34,7 @@ enum {
#define R_DACSR 0x19
#define R_PWRM1 0x1A
#define R_PWRM2 0x1B
+#define R_CTL 0x1C
#define R_CONFIG0 0x1F
#define R_CONFIG1 0x20
#define R_DMICCTL 0x24
@@ -1110,6 +1111,13 @@ enum {
#define RV_PWRM2_VREF_DISABLE \
RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
+/******************************
+ * R_CTL (0x1C) *
+ ******************************/
+
+/* Fiel Offsets */
+#define FB_CTL_HPSWEN 7
+#define FB_CTL_HPSWPOL 6
/******************************
* R_CONFIG0 (0x1F) *