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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-03-02 11:34:27 +0300 |
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committer | Mark Brown <broonie@kernel.org> | 2022-03-07 16:13:09 +0300 |
commit | 1d4cbdf7bf2eaa794528250a29aed08f1df7f837 (patch) | |
tree | 2074ea987682d6faeceba7a245cb7c6580cf54e7 /sound/soc/fsl/fsl_sai.c | |
parent | c56359f4f2adfb81cf7cbea1e8ef9bfc59dbd4ec (diff) | |
download | linux-1d4cbdf7bf2eaa794528250a29aed08f1df7f837.tar.xz |
ASoC: fsl_sai: use DIV_ROUND_CLOSEST() to calculate divider
In fsl_sai_set_bclk() we want to calculate the divider that gets us
closest to the desired frequency, so use DIV_ROUND_CLOSEST() instead of
just doing a clk_rate/freq.
Also discard invalid ratios earlier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-7-s.hauer@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl/fsl_sai.c')
-rw-r--r-- | sound/soc/fsl/fsl_sai.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 02b4cffa8455..761fa8229a09 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -366,9 +366,11 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) if (!clk_rate) continue; - ratio = clk_rate / freq; + ratio = DIV_ROUND_CLOSEST(clk_rate, freq); + if (!ratio || ratio > 512 || ratio & 1) + continue; - diff = clk_rate - ratio * freq; + diff = abs((long)clk_rate - ratio * freq); /* * Drop the source that can not be @@ -381,10 +383,6 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) "ratio %d for freq %dHz based on clock %ldHz\n", ratio, freq, clk_rate); - if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) - ratio /= 2; - else - continue; if (diff < bestdiff) { savediv = ratio; @@ -424,7 +422,7 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); - regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv - 1); + regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv / 2 - 1); return 0; } |