diff options
| author | Axel Lin <axel.lin@gmail.com> | 2011-10-13 10:57:31 +0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-10-13 14:50:05 +0400 |
| commit | edf413f689e930011bf39ec726f704af99d7263b (patch) | |
| tree | 1883284699350a46737dfd9c3fd6f6baf9d3179d /sound/soc/codecs/sta32x.c | |
| parent | f0bbc2b55f47f93286bb1b9ddbdb8ffed3572064 (diff) | |
| download | linux-edf413f689e930011bf39ec726f704af99d7263b.tar.xz | |
ASoC: sta32x: Write the register default value to cache for reserved registers
Chip documentation explicitly requires that the reset values
of reserved register bits are left untouched.
codec->hw_read is broken now.
Here we use below trick to avoid writing to reserved registers while resume.
Write the register default value to cache for reserved registers,
so the write to the these registers are suppressed by the cache
restore code when it skips writes of default registers.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/sta32x.c')
| -rw-r--r-- | sound/soc/codecs/sta32x.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c index 754b3ff9afa5..bb82408ab8e1 100644 --- a/sound/soc/codecs/sta32x.c +++ b/sound/soc/codecs/sta32x.c @@ -756,21 +756,19 @@ static int sta32x_probe(struct snd_soc_codec *codec) return ret; } - /* preserve reset values of reserved register bits */ - snd_soc_cache_write(codec, STA32X_CONFC, - codec->hw_read(codec, STA32X_CONFC)); - snd_soc_cache_write(codec, STA32X_CONFE, - codec->hw_read(codec, STA32X_CONFE)); - snd_soc_cache_write(codec, STA32X_CONFF, - codec->hw_read(codec, STA32X_CONFF)); - snd_soc_cache_write(codec, STA32X_MMUTE, - codec->hw_read(codec, STA32X_MMUTE)); - snd_soc_cache_write(codec, STA32X_AUTO1, - codec->hw_read(codec, STA32X_AUTO1)); - snd_soc_cache_write(codec, STA32X_AUTO3, - codec->hw_read(codec, STA32X_AUTO3)); - snd_soc_cache_write(codec, STA32X_C3CFG, - codec->hw_read(codec, STA32X_C3CFG)); + /* Chip documentation explicitly requires that the reset values + * of reserved register bits are left untouched. + * Write the register default value to cache for reserved registers, + * so the write to the these registers are suppressed by the cache + * restore code when it skips writes of default registers. + */ + snd_soc_cache_write(codec, STA32X_CONFC, 0xc2); + snd_soc_cache_write(codec, STA32X_CONFE, 0xc2); + snd_soc_cache_write(codec, STA32X_CONFF, 0x5c); + snd_soc_cache_write(codec, STA32X_MMUTE, 0x10); + snd_soc_cache_write(codec, STA32X_AUTO1, 0x60); + snd_soc_cache_write(codec, STA32X_AUTO3, 0x00); + snd_soc_cache_write(codec, STA32X_C3CFG, 0x40); /* FIXME enable thermal warning adjustment and recovery */ snd_soc_update_bits(codec, STA32X_CONFA, |