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| author | Richard Fitzgerald <rf@opensource.cirrus.com> | 2023-04-18 17:43:07 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-04-18 19:09:14 +0300 |
| commit | 5ab28c78a125a724684958f4caf8210127d3f528 (patch) | |
| tree | 409ed35d282c88bd575a4bcbcd45a8ab58b56ee1 /sound/soc/codecs/cs35l56-shared.c | |
| parent | 16e5fc8ae793947d7dd0de63c7a613798f75c237 (diff) | |
| download | linux-5ab28c78a125a724684958f4caf8210127d3f528.tar.xz | |
ASoC: cs35l56: Remove SDW1 TX5 and TX6
Reduce SDW1 to 4 channels and remove the controls for SDW1
TX5 and TX6.
The TX5 and TX6 channels have been removed from B0 silicon.
There is no need to support them on A1 silicon.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230418144309.1100721-3-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/cs35l56-shared.c')
| -rw-r--r-- | sound/soc/codecs/cs35l56-shared.c | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/sound/soc/codecs/cs35l56-shared.c b/sound/soc/codecs/cs35l56-shared.c index d8bc06ad4888..f5fa6bb04d38 100644 --- a/sound/soc/codecs/cs35l56-shared.c +++ b/sound/soc/codecs/cs35l56-shared.c @@ -28,8 +28,6 @@ static const struct reg_default cs35l56_reg_defaults[] = { { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, - { CS35L56_SWIRE_DP3_CH5_INPUT, 0x00000018 }, - { CS35L56_SWIRE_DP3_CH6_INPUT, 0x00000018 }, { CS35L56_IRQ1_CFG, 0x00000000 }, { CS35L56_IRQ1_MASK_1, 0x83ffffff }, { CS35L56_IRQ1_MASK_2, 0xffff7fff }, @@ -42,29 +40,6 @@ static const struct reg_default cs35l56_reg_defaults[] = { /* CS35L56_MAIN_POSTURE_NUMBER - soft register, no default */ }; -/* - * The Ax devices have different default register values to that of B0, - * establish a common set of register defaults. - */ -static const struct reg_sequence cs35l56_reva_patch[] = { - { CS35L56_SWIRE_DP3_CH5_INPUT, 0x00000018 }, - { CS35L56_SWIRE_DP3_CH6_INPUT, 0x00000018 }, -}; - -void cs35l56_patch(struct device *dev, struct regmap *regmap, u8 revid) -{ - int ret; - - if (revid >= CS35L56_REVID_B0) - return; - - ret = regmap_register_patch(regmap, cs35l56_reva_patch, - ARRAY_SIZE(cs35l56_reva_patch)); - if (ret) - dev_err(dev, "Failed to apply patch: %d\n", ret); -} -EXPORT_SYMBOL_NS_GPL(cs35l56_patch, SND_SOC_CS35L56_SHARED); - static bool cs35l56_is_dsp_memory(unsigned int reg) { switch (reg) { @@ -114,8 +89,6 @@ static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) case CS35L56_SWIRE_DP3_CH2_INPUT: case CS35L56_SWIRE_DP3_CH3_INPUT: case CS35L56_SWIRE_DP3_CH4_INPUT: - case CS35L56_SWIRE_DP3_CH5_INPUT: - case CS35L56_SWIRE_DP3_CH6_INPUT: case CS35L56_IRQ1_CFG: case CS35L56_IRQ1_STATUS: case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: |