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| author | Shreyas NC <shreyas.nc@intel.com> | 2018-07-27 12:14:17 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2018-08-27 07:19:48 +0300 |
| commit | 30246e2d78c0b06d67f77c4239f6741e77f42185 (patch) | |
| tree | 535d0624bf087e73dc245a53218009f882bad61c /scripts/gdb/linux/utils.py | |
| parent | 9b5c132a1ec98895fe40ba73a19e0a17293122e5 (diff) | |
| download | linux-30246e2d78c0b06d67f77c4239f6741e77f42185.tar.xz | |
soundwire: intel: Add pre/post bank switch ops
To support multi link on Intel platforms, we need to update
SDW SHIM registers.
So, add pre/post bank switch ops for the same in Intel driver.
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Shreyas NC <shreyas.nc@intel.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions