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| author | Tao Xu <tao3.xu@intel.com> | 2019-07-16 09:55:50 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-09-24 15:34:36 +0300 |
| commit | 6e3ba4abcea5681eebbfc10f1b56c9fbe80b6685 (patch) | |
| tree | 98719f3f207dfe3d8ef0b8125c56b6ea2dca02de /scripts/gdb/linux/proc.py | |
| parent | e69e72faa3a0709dd23df6a4ca060a15e99168a1 (diff) | |
| download | linux-6e3ba4abcea5681eebbfc10f1b56c9fbe80b6685.tar.xz | |
KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
UMWAIT and TPAUSE instructions use 32bit IA32_UMWAIT_CONTROL at MSR index
E1H to determines the maximum time in TSC-quanta that the processor can
reside in either C0.1 or C0.2.
This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
IA32_UMWAIT_CONTROL between host and guest. The variable
mwait_control_cached in arch/x86/kernel/cpu/umwait.c caches the MSR value,
so this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions