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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-02-24 13:11:04 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-03-01 02:02:15 +0300 |
| commit | dae320ec31736865d22bfac78717726b6545ff41 (patch) | |
| tree | 727c00770423f7513af069014f376aa65eb89c0a /scripts/gdb/linux/modules.py | |
| parent | 4d91e285483bf6a93d84a483ec0921b86bbc3d24 (diff) | |
| download | linux-dae320ec31736865d22bfac78717726b6545ff41.tar.xz | |
ARM: dts: DRA7: change address-cells and size-cells
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions