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| author | Marek Vasut <marex@denx.de> | 2021-09-07 05:38:29 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-04 10:53:01 +0300 |
| commit | 34a01d9ea7c4981e19c9e926f5e293b011ecd5a3 (patch) | |
| tree | 7039e6391194c81573b102de786b2cfd861daeee /mm/dmapool.c | |
| parent | 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f (diff) | |
| download | linux-34a01d9ea7c4981e19c9e926f5e293b011ecd5a3.tar.xz | |
soc: imx: gpcv2: Turn domain->pgc into bitfield
There is currently the MX8MM GPU domain, which is in fact a composite domain
for both GPU2D and GPU3D. To correctly configure this domain, it is necessary
to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same
time. This is currently not possible.
Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
register array. This way it is possible to configure all GPC_PGC_nCTRL
registers required in a particular domain.
This is a preparatory patch, no functional change.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'mm/dmapool.c')
0 files changed, 0 insertions, 0 deletions