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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-12-07 15:35:39 +0300 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2021-12-08 17:29:22 +0300 |
| commit | f872f73601b92c86f3da8bdf3e19abd0f1780eb9 (patch) | |
| tree | 207079d25254d554724c26a2c32c87b62f3de261 /mm/compaction.c | |
| parent | 0fcfb00b28c0b7884635dacf38e46d60bf3d4eb1 (diff) | |
| download | linux-f872f73601b92c86f3da8bdf3e19abd0f1780eb9.tar.xz | |
thermal: int340x: Fix VCoRefLow MMIO bit offset for TGL
The VCoRefLow CPU FIVR register definition for Tiger Lake is incorrect.
Current implementation reads it from MMIO offset 0x5A18 and bit
offset [12:14], but the actual correct register definition is from
bit offset [11:13].
Update to fix the bit offset.
Fixes: 473be51142ad ("thermal: int340x: processor_thermal: Add RFIM driver")
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Cc: 5.14+ <stable@vger.kernel.org> # 5.14+
[ rjw: New subject, changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'mm/compaction.c')
0 files changed, 0 insertions, 0 deletions