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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2019-07-27 15:04:15 +0300
committerPaul Burton <paul.burton@mips.com>2019-08-24 17:13:22 +0300
commited90302be64a53d9031c8ce05428c358b16a5d96 (patch)
tree3e009ab59e56d5d39eed89481679cd13ffc392be /lib/cmdline.c
parent12051b318bc3ce5b42d6d786191008284b067d83 (diff)
downloadlinux-ed90302be64a53d9031c8ce05428c358b16a5d96.tar.xz
MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver
The mainline PCIe PHY driver has it's own devicetree node. Update the clock alias so the mainline driver finds the clocks. The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300 and GRX390. The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and GRX390. The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390. Lantiq's board support package (called "UGW") names these registers "PDI". Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: john@phrozen.org Cc: kishon@ti.com Cc: ralf@linux-mips.org Cc: robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org Cc: hauke@hauke-m.de Cc: mark.rutland@arm.com Cc: ms@dev.tdt.de
Diffstat (limited to 'lib/cmdline.c')
0 files changed, 0 insertions, 0 deletions