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authorPeter 'p2' De Schrijver <peter.de-schrijver@nokia.com>2010-12-20 23:05:07 +0300
committerKevin Hilman <khilman@deeprootsystems.com>2010-12-22 01:45:51 +0300
commitc4236d2e7913d18d058a018f0d19473eb6a11a3c (patch)
treeb90600a00f6dd27eb03f7a278a5959a5f7d5b6a6 /kernel
parent458e999eb14a301d4176783c8fcb277f5d009b4e (diff)
downloadlinux-c4236d2e7913d18d058a018f0d19473eb6a11a3c.tar.xz
OMAP3630: PM: Disable L2 cache while invalidating L2 cache
While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'kernel')
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