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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-26 06:26:54 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-26 06:26:54 +0400 |
| commit | b394209ce528b6a6e76c6460300781981140d207 (patch) | |
| tree | a3263cca4f4ea9b79e3ea2696cc6dd99d1decf91 /include | |
| parent | fec4fba6e44407cfbdeed7d48f6f37e6ddfe19d7 (diff) | |
| parent | 96fb1a241de128d75d5335c24392b065033c2dbe (diff) | |
| download | linux-b394209ce528b6a6e76c6460300781981140d207.tar.xz | |
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm radeon fixes from Dave Airlie:
"Just radeon fixes in this one:
- some new PCI IDs
- ATPX regression fix
- async VM regression fixes
- some module options fixes"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: fix ATPX regression in acpi rework
drm/radeon: fix ATPX function documentation
drm/radeon: move the retry to gem_object_create
drm/radeon: move size limits to gem_object_create.
drm/radeon: use vzalloc for gart pages
drm/radeon: fix and simplify pot argument checks v3
drm/radeon: fix header size estimation in VM code
drm/radeon: remove set_page check from VM code
drm/radeon: fix si_set_page v2
drm/radeon: fix cayman_vm_set_page v2
drm/radeon: fix PFP sync in vm_flush
drm/radeon: add error output if VM CS fails on cayman
drm/radeon: give each backlight a unique id
drm/radeon: fix sparse warning
drm/radeon: add some new SI PCI ids
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm/drm_pciids.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index c78bb997e2c6..af1cbaf535ed 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -205,6 +205,8 @@ {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ @@ -217,6 +219,7 @@ {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |