dts: moving the dts files from Uboot to kernel

Keep the same dts file with Uboot vic_starlight branch which attach to the
5.10 kernel

Signed-off-by: Andy Hu <andy.hu@starfivetech.com>

3 files changed, 294 insertions, 241 deletions

diff --git a/include/dt-bindings/clock/starfive-jh7100-clkgen.h b/include/dt-bindings/clock/starfive-jh7100-clkgen.h
deleted file mode 100644
index 34c307adb017..000000000000
--- a/include/dt-bindings/clock/starfive-jh7100-clkgen.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR X11 */
-/*
- * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
- */
-
-#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
-#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
-
-#define JH7100_CLK_OSC_SYS		0
-#define JH7100_CLK_OSC_AUD		1
-#define JH7100_CLK_PLL0_OUT		2
-#define JH7100_CLK_PLL1_OUT		3
-#define JH7100_CLK_PLL2_OUT		4
-#define JH7100_CLK_CPUNDBUS_ROOT	5
-#define JH7100_CLK_DLA_ROOT		6
-#define JH7100_CLK_DSP_ROOT		7
-#define JH7100_CLK_GMACUSB_ROOT		8
-#define JH7100_CLK_PERH0_ROOT		9
-#define JH7100_CLK_PERH1_ROOT		10
-#define JH7100_CLK_VIN_ROOT		11
-#define JH7100_CLK_VOUT_ROOT		12
-#define JH7100_CLK_AUDIO_ROOT		13
-#define JH7100_CLK_CDECHIFI4_ROOT	14
-#define JH7100_CLK_CDEC_ROOT		15
-#define JH7100_CLK_VOUTBUS_ROOT		16
-#define JH7100_CLK_CPUNBUS_ROOT_DIV	17
-#define JH7100_CLK_DSP_ROOT_DIV		18
-#define JH7100_CLK_PERH0_SRC		19
-#define JH7100_CLK_PERH1_SRC		20
-#define JH7100_CLK_PLL0_TESTOUT		21
-#define JH7100_CLK_PLL1_TESTOUT		22
-#define JH7100_CLK_PLL2_TESTOUT		23
-#define JH7100_CLK_PLL2_REF		24
-#define JH7100_CLK_CPU_CORE		25
-#define JH7100_CLK_CPU_AXI		26
-#define JH7100_CLK_AHB_BUS		27
-#define JH7100_CLK_APB1_BUS		28
-#define JH7100_CLK_APB2_BUS		29
-#define JH7100_CLK_DOM3AHB_BUS		30
-#define JH7100_CLK_DOM7AHB_BUS		31
-#define JH7100_CLK_U74_CORE0		32
-#define JH7100_CLK_U74_CORE1		33
-#define JH7100_CLK_U74_AXI		34
-#define JH7100_CLK_U74RTC_TOGGLE	35
-#define JH7100_CLK_SGDMA2P_AXI		36
-#define JH7100_CLK_DMA2PNOC_AXI		37
-#define JH7100_CLK_SGDMA2P_AHB		38
-#define JH7100_CLK_DLA_BUS		39
-#define JH7100_CLK_DLA_AXI		40
-#define JH7100_CLK_DLANOC_AXI		41
-#define JH7100_CLK_DLA_APB		42
-#define JH7100_CLK_VP6_CORE		43
-#define JH7100_CLK_VP6BUS_SRC		44
-#define JH7100_CLK_VP6_AXI		45
-#define JH7100_CLK_VCDECBUS_SRC		46
-#define JH7100_CLK_VDEC_BUS		47
-#define JH7100_CLK_VDEC_AXI		48
-#define JH7100_CLK_VDECBRG_MAIN		49
-#define JH7100_CLK_VDEC_BCLK		50
-#define JH7100_CLK_VDEC_CCLK		51
-#define JH7100_CLK_VDEC_APB		52
-#define JH7100_CLK_JPEG_AXI		53
-#define JH7100_CLK_JPEG_CCLK		54
-#define JH7100_CLK_JPEG_APB		55
-#define JH7100_CLK_GC300_2X		56
-#define JH7100_CLK_GC300_AHB		57
-#define JH7100_CLK_JPCGC300_AXIBUS	58
-#define JH7100_CLK_GC300_AXI		59
-#define JH7100_CLK_JPCGC300_MAIN	60
-#define JH7100_CLK_VENC_BUS		61
-#define JH7100_CLK_VENC_AXI		62
-#define JH7100_CLK_VENCBRG_MAIN		63
-#define JH7100_CLK_VENC_BCLK		64
-#define JH7100_CLK_VENC_CCLK		65
-#define JH7100_CLK_VENC_APB		66
-#define JH7100_CLK_DDRPLL_DIV2		67
-#define JH7100_CLK_DDRPLL_DIV4		68
-#define JH7100_CLK_DDRPLL_DIV8		69
-#define JH7100_CLK_DDROSC_DIV2		70
-#define JH7100_CLK_DDRC0		71
-#define JH7100_CLK_DDRC1		72
-#define JH7100_CLK_DDRPHY_APB		73
-#define JH7100_CLK_NOC_ROB		74
-#define JH7100_CLK_NOC_COG		75
-#define JH7100_CLK_NNE_AHB		76
-#define JH7100_CLK_NNEBUS_SRC1		77
-#define JH7100_CLK_NNE_BUS		78
-#define JH7100_CLK_NNE_AXI		79
-#define JH7100_CLK_NNENOC_AXI		80
-#define JH7100_CLK_DLASLV_AXI		81
-#define JH7100_CLK_DSPX2C_AXI		82
-#define JH7100_CLK_HIFI4_SRC		83
-#define JH7100_CLK_HIFI4_COREFREE	84
-#define JH7100_CLK_HIFI4_CORE		85
-#define JH7100_CLK_HIFI4_BUS		86
-#define JH7100_CLK_HIFI4_AXI		87
-#define JH7100_CLK_HIFI4NOC_AXI		88
-#define JH7100_CLK_SGDMA1P_BUS		89
-#define JH7100_CLK_SGDMA1P_AXI		90
-#define JH7100_CLK_DMA1P_AXI		91
-#define JH7100_CLK_X2C_AXI		92
-#define JH7100_CLK_USB_BUS		93
-#define JH7100_CLK_USB_AXI		94
-#define JH7100_CLK_USBNOC_AXI		95
-#define JH7100_CLK_USBPHY_ROOTDIV	96
-#define JH7100_CLK_USBPHY_125M		97
-#define JH7100_CLK_USBPHY_PLLDIV25M	98
-#define JH7100_CLK_USBPHY_25M		99
-#define JH7100_CLK_AUDIO_DIV		100
-#define JH7100_CLK_AUDIO_SRC		101
-#define JH7100_CLK_AUDIO_12288		102
-#define JH7100_CLK_VIN_SRC		103
-#define JH7100_CLK_ISP0_BUS		104
-#define JH7100_CLK_ISP0_AXI		105
-#define JH7100_CLK_ISP0NOC_AXI		106
-#define JH7100_CLK_ISPSLV_AXI		107
-#define JH7100_CLK_ISP1_BUS		108
-#define JH7100_CLK_ISP1_AXI		109
-#define JH7100_CLK_ISP1NOC_AXI		110
-#define JH7100_CLK_VIN_BUS		111
-#define JH7100_CLK_VIN_AXI		112
-#define JH7100_CLK_VINNOC_AXI		113
-#define JH7100_CLK_VOUT_SRC		114
-#define JH7100_CLK_DISPBUS_SRC		115
-#define JH7100_CLK_DISP_BUS		116
-#define JH7100_CLK_DISP_AXI		117
-#define JH7100_CLK_DISPNOC_AXI		118
-#define JH7100_CLK_SDIO0_AHB		119
-#define JH7100_CLK_SDIO0_CCLKINT	120
-#define JH7100_CLK_SDIO0_CCLKINT_INV	121
-#define JH7100_CLK_SDIO1_AHB		122
-#define JH7100_CLK_SDIO1_CCLKINT	123
-#define JH7100_CLK_SDIO1_CCLKINT_INV	124
-#define JH7100_CLK_GMAC_AHB		125
-#define JH7100_CLK_GMAC_ROOT_DIV	126
-#define JH7100_CLK_GMAC_PTP_REF		127
-#define JH7100_CLK_GMAC_GTX		128
-#define JH7100_CLK_GMAC_RMII_TX		129
-#define JH7100_CLK_GMAC_RMII_RX		130
-#define JH7100_CLK_GMAC_TX		131
-#define JH7100_CLK_GMAC_TX_INV		132
-#define JH7100_CLK_GMAC_RX_PRE		133
-#define JH7100_CLK_GMAC_RX_INV		134
-#define JH7100_CLK_GMAC_RMII		135
-#define JH7100_CLK_GMAC_TOPHYREF	136
-#define JH7100_CLK_SPI2AHB_AHB		137
-#define JH7100_CLK_SPI2AHB_CORE		138
-#define JH7100_CLK_EZMASTER_AHB		139
-#define JH7100_CLK_E24_AHB		140
-#define JH7100_CLK_E24RTC_TOGGLE	141
-#define JH7100_CLK_QSPI_AHB		142
-#define JH7100_CLK_QSPI_APB		143
-#define JH7100_CLK_QSPI_REF		144
-#define JH7100_CLK_SEC_AHB		145
-#define JH7100_CLK_AES			146
-#define JH7100_CLK_SHA			147
-#define JH7100_CLK_PKA			148
-#define JH7100_CLK_TRNG_APB		149
-#define JH7100_CLK_OTP_APB		150
-#define JH7100_CLK_UART0_APB		151
-#define JH7100_CLK_UART0_CORE		152
-#define JH7100_CLK_UART1_APB		153
-#define JH7100_CLK_UART1_CORE		154
-#define JH7100_CLK_SPI0_APB		155
-#define JH7100_CLK_SPI0_CORE		156
-#define JH7100_CLK_SPI1_APB		157
-#define JH7100_CLK_SPI1_CORE		158
-#define JH7100_CLK_I2C0_APB		159
-#define JH7100_CLK_I2C0_CORE		160
-#define JH7100_CLK_I2C1_APB		161
-#define JH7100_CLK_I2C1_CORE		162
-#define JH7100_CLK_GPIO_APB		163
-#define JH7100_CLK_UART2_APB		164
-#define JH7100_CLK_UART2_CORE		165
-#define JH7100_CLK_UART3_APB		166
-#define JH7100_CLK_UART3_CORE		167
-#define JH7100_CLK_SPI2_APB		168
-#define JH7100_CLK_SPI2_CORE		169
-#define JH7100_CLK_SPI3_APB		170
-#define JH7100_CLK_SPI3_CORE		171
-#define JH7100_CLK_I2C2_APB		172
-#define JH7100_CLK_I2C2_CORE		173
-#define JH7100_CLK_I2C3_APB		174
-#define JH7100_CLK_I2C3_CORE		175
-#define JH7100_CLK_WDTIMER_APB		176
-#define JH7100_CLK_WDT_CORE		177
-#define JH7100_CLK_TIMER0_CORE		178
-#define JH7100_CLK_TIMER1_CORE		179
-#define JH7100_CLK_TIMER2_CORE		180
-#define JH7100_CLK_TIMER3_CORE		181
-#define JH7100_CLK_TIMER4_CORE		182
-#define JH7100_CLK_TIMER5_CORE		183
-#define JH7100_CLK_TIMER6_CORE		184
-#define JH7100_CLK_VP6INTC_APB		185
-#define JH7100_CLK_PWM_APB		186
-#define JH7100_CLK_MSI_APB		187
-#define JH7100_CLK_TEMP_APB		188
-#define JH7100_CLK_TEMP_SENSE		189
-#define JH7100_CLK_SYSERR_APB		190
-
-#define JH7100_CLK_SYS_MAX		191
-
-
-/* audio */
-#define JH7100_CLK_ADC_MCLK		0
-#define JH7100_CLK_I2S1_MCLK		1
-#define JH7100_CLK_APB_I2SADC_EN	2
-#define JH7100_CLK_I2SADC_BCLK		3
-#define JH7100_CLK_I2SADC_BCLK_INV	4
-#define JH7100_CLK_I2SADC_LRCLK		5
-#define JH7100_CLK_APB_PDM_EN		6
-#define JH7100_CLK_PDM_MCLK		7
-#define JH7100_CLK_APB_I2SVAD_EN	8
-#define JH7100_CLK_SPDIF		9
-#define JH7100_CLK_APB_SPDIF_EN		10
-#define JH7100_CLK_APB_PWMDAC_EN	11
-#define JH7100_CLK_DAC_MCLK		12
-#define JH7100_CLK_APB_I2S0_EN		13
-#define JH7100_CLK_I2S0_BCLK		14
-#define JH7100_CLK_I2S0_BCLK_INV	15
-#define JH7100_CLK_I2S0_LRCLK		16
-#define JH7100_CLK_APB_I2S1_EN		17
-#define JH7100_CLK_I2S1_BCLK		18
-#define JH7100_CLK_I2S1_BCLK_INV	19
-#define JH7100_CLK_I2S1_LRCLK		20
-#define JH7100_CLK_ADC_BCLK_IO		21
-#define JH7100_CLK_ADC_LRCLK_IO		22
-#define JH7100_CLK_DAC0_BCLK_IO		23
-#define JH7100_CLK_DAC0_LRCLK_IO	24
-#define JH7100_CLK_DAC1_BCLK_IO		25
-#define JH7100_CLK_DAC1_LRCLK_IO	26
-#define JH7100_CLK_CODEC_EXT		27
-#define JH7100_CLK_AUD_12288		28
-
-#define JH7100_CLK_AUD_MAX		29
-
-
-#define JH7100_CLK_ISP_MAX		0
-
-#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */
-
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive.h b/include/dt-bindings/pinctrl/pinctrl-starfive.h
new file mode 100755
index 000000000000..94011554e608
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive.h
@@ -0,0 +1,247 @@
+#ifndef _DT_BINDINGS_VIC7100_PINCTRL_STARFIVE_H
+#define _DT_BINDINGS_VIC7100_PINCTRL_STARFIVE_H
+
+//gpo(n)_dout/doen signal pool  DOUT(signal pool)/DOEN(signal pool)
+#define GPO_DOUT_LOW			0
+#define GPO_DOUT_HIGH			1
+#define GPO_DOEN_OUTPUT			0
+#define GPO_DOEN_INPUT			1
+
+#define GPO_CLK_GMAC_PAPHYREF		2
+#define GPO_JTAG_TDO			3
+#define GPO_JTAG_TDO_OEN		4
+#define GPO_DMIC_CLK_OUT		5
+#define GPO_DSP_JTDOEN			6
+#define GPO_DSP_JTDO			7
+#define GPO_I2C0_SCK_OE			8
+#define GPO_I2C0_SDA_OE			9
+#define GPO_I2C1_SCK_OE			10
+#define GPO_I2C1_SDA_OE			11
+#define GPO_I2C2_SCK_OE			12
+#define GPO_I2C2_SDA_OE			13
+#define GPO_I2C3_SCK_OE			14
+#define GPO_I2C3_SDA_OE			15
+#define GPO_I2SRX_BCLK_OUT		16
+#define GPO_I2SRX_BCLK_OUT_OEN		17
+#define GPO_I2SRX_LRCK_OUT		18
+#define GPO_I2SRX_LRCK_OUT_OEN		19
+#define GPO_I2SRX_MCLK_OUT		20
+#define GPO_I2STX_BCLK_OUT		21
+#define GPO_I2STX_BCLK_OUT_OEN		22
+#define GPO_I2STX_LRCK_OUT		23
+#define GPO_I2STX_LRCK_OUT_OEN		24
+#define GPO_I2STX_MCLK_OUT		25
+#define GPO_I2STX_SDOUT0		26
+#define GPO_I2STX_SDOUT1		27
+#define GPO_LCD_CSM_N			28
+#define GPO_PWM_OE_N_BIT0		29
+#define GPO_PWM_OE_N_BIT1		30
+#define GPO_PWM_OE_N_BIT2		31
+#define GPO_PWM_OE_N_BIT3		32
+#define GPO_PWM_OE_N_BIT4		33
+#define GPO_PWM_OE_N_BIT5		34
+#define GPO_PWM_OE_N_BIT6		35
+#define GPO_PWM_OE_N_BIT7		36
+#define GPO_PWM_OUT_BIT0		37
+#define GPO_PWM_OUT_BIT1		38
+#define GPO_PWM_OUT_BIT2		39
+#define GPO_PWM_OUT_BIT3		40
+#define GPO_PWM_OUT_BIT4		41
+#define GPO_PWM_OUT_BIT5		42
+#define GPO_PWM_OUT_BIT6		43
+#define GPO_PWM_OUT_BIT7		44
+#define GPO_PWMDAC_LEFT_OUT		45
+#define GPO_PWMDAC_RIGHT_OUT		46
+#define GPO_QSPI_CSN1_OUT		47
+#define GPO_QSPI_CSN2_OUT		48
+#define GPO_QSPI_CSN3_OUT		49
+#define GPO_REGISTER23_SCFG_CMSENSOR_RST0		50
+#define GPO_REGISTER23_SCFG_CMSENSOR_RST1		51
+#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN		52
+#define GPO_SDIO0_CARD_POWER_EN		53
+#define GPO_SDIO0_CCLK_OUT		54
+#define GPO_SDIO0_CCMD_OE		55
+#define GPO_SDIO0_CCMD_OUT		56
+#define GPO_SDIO0_CDATA_OE_BIT0		57
+#define GPO_SDIO0_CDATA_OE_BIT1		58
+#define GPO_SDIO0_CDATA_OE_BIT2		59
+#define GPO_SDIO0_CDATA_OE_BIT3		60
+#define GPO_SDIO0_CDATA_OE_BIT4		61
+#define GPO_SDIO0_CDATA_OE_BIT5		62
+#define GPO_SDIO0_CDATA_OE_BIT6		63
+#define GPO_SDIO0_CDATA_OE_BIT7		64
+#define GPO_SDIO0_CDATA_OUT_BIT0	65
+#define GPO_SDIO0_CDATA_OUT_BIT1	66
+#define GPO_SDIO0_CDATA_OUT_BIT2	67
+#define GPO_SDIO0_CDATA_OUT_BIT3	68
+#define GPO_SDIO0_CDATA_OUT_BIT4	69
+#define GPO_SDIO0_CDATA_OUT_BIT5	70
+#define GPO_SDIO0_CDATA_OUT_BIT6	71
+#define GPO_SDIO0_CDATA_OUT_BIT7	72
+#define GPO_SDIO0_RST_N			73
+#define GPO_SDIO1_CARD_POWER_EN		74
+#define GPO_SDIO1_CCLK_OUT		75
+#define GPO_SDIO1_CCMD_OE		76
+#define GPO_SDIO1_CCMD_OUT		77
+#define GPO_SDIO1_CDATA_OE_BIT0		78
+#define GPO_SDIO1_CDATA_OE_BIT1		79
+#define GPO_SDIO1_CDATA_OE_BIT2		80
+#define GPO_SDIO1_CDATA_OE_BIT3		81
+#define GPO_SDIO1_CDATA_OE_BIT4		82
+#define GPO_SDIO1_CDATA_OE_BIT5		83
+#define GPO_SDIO1_CDATA_OE_BIT6		84
+#define GPO_SDIO1_CDATA_OE_BIT7		85
+#define GPO_SDIO1_CDATA_OUT_BIT0	86
+#define GPO_SDIO1_CDATA_OUT_BIT1	87
+#define GPO_SDIO1_CDATA_OUT_BIT2	88
+#define GPO_SDIO1_CDATA_OUT_BIT3	89
+#define GPO_SDIO1_CDATA_OUT_BIT4	90
+#define GPO_SDIO1_CDATA_OUT_BIT5	91
+#define GPO_SDIO1_CDATA_OUT_BIT6	92
+#define GPO_SDIO1_CDATA_OUT_BIT7	93
+#define GPO_SDIO1_RST_N			94
+#define GPO_SPDIF_TX_SDOUT		95
+#define GPO_SPDIF_TX_SDOUT_OEN		96
+#define GPO_SPI0_OE_N			97
+#define GPO_SPI0_SCK_OUT		98
+#define GPO_SPI0_SS_0_N			99
+#define GPO_SPI0_SS_1_N			100
+#define GPO_SPI0_TXD			101
+#define GPO_SPI1_OE_N			102
+#define GPO_SPI1_SCK_OUT		103
+#define GPO_SPI1_SS_0_N			104
+#define GPO_SPI1_SS_1_N			105
+#define GPO_SPI1_TXD			106
+#define GPO_SPI2_OE_N			107
+#define GPO_SPI2_SCK_OUT		108
+#define GPO_SPI2_SS_0_N			109
+#define GPO_SPI2_SS_1_N			110
+#define GPO_SPI2_TXD			111
+#define GPO_SPI2AHB_OE_N_BIT0		112
+#define GPO_SPI2AHB_OE_N_BIT1		113
+#define GPO_SPI2AHB_OE_N_BIT2		114
+#define GPO_SPI2AHB_OE_N_BIT3		115
+#define GPO_SPI2AHB_TXD_BIT0		116
+#define GPO_SPI2AHB_TXD_BIT1		117
+#define GPO_SPI2AHB_TXD_BIT2		118
+#define GPO_SPI2AHB_TXD_BIT3		119
+#define GPO_SPI3_OE_N			120
+#define GPO_SPI3_SCK_OUT		121
+#define GPO_SPI3_SS_0_N			122
+#define GPO_SPI3_SS_1_N			123
+#define GPO_SPI3_TXD			124
+#define GPO_UART0_DTRN			125
+#define GPO_UART0_RTSN			126
+#define GPO_UART0_SOUT			127
+#define GPO_UART1_SOUT			128
+#define GPO_UART2_DTR_N			129
+#define GPO_UART2_RTS_N			130
+#define GPO_UART2_SOUT			131
+#define GPO_UART3_SOUT			132
+#define GPO_USB_DRV_BUS			133
+
+
+//gpi(n)signal pool offset address   DIN(signal pool offset address)
+#define GPI_CPU_JTAG_TCK		0
+#define GPI_CPU_JTAG_TDI		1
+#define GPI_CPU_JTAG_TMS		2
+#define GPI_CPU_JTAG_TRST		3
+#define GPI_DMIC_SDIN_BIT0		4
+#define GPI_DMIC_SDIN_BIT1		5
+#define GPI_DSP_JTCK			6
+#define GPI_DSP_JTDI			7
+#define GPI_DSP_JTMS			8
+#define GPI_DSP_TRST			9
+#define GPI_I2C0_SCK_IN			10
+#define GPI_I2C0_SDA_IN			11
+#define GPI_I2C1_SCK_IN			12
+#define GPI_I2C1_SDA_IN			13
+#define GPI_I2C2_SCK_IN			14
+#define GPI_I2C2_SDA_IN			15
+#define GPI_I2C3_SCK_IN			16
+#define GPI_I2C3_SDA_IN			17
+#define GPI_I2SRX_BCLK_IN		18
+#define GPI_I2SRX_LRCK_IN		19
+#define GPI_I2SRX_SDIN_BIT0		20
+#define GPI_I2SRX_SDIN_BIT1		21
+#define GPI_I2SRX_SDIN_BIT2		22
+#define GPI_I2STX_BCLK_IN		23
+#define GPI_I2STX_LRCK_IN		24
+#define GPI_SDIO0_CARD_DETECT_N		25
+#define GPI_SDIO0_CARD_WRITE_PRT	26
+#define GPI_SDIO0_CCMD_IN		27
+#define GPI_SDIO0_CDATA_IN_BIT0		28
+#define GPI_SDIO0_CDATA_IN_BIT1		29
+#define GPI_SDIO0_CDATA_IN_BIT2		30
+#define GPI_SDIO0_CDATA_IN_BIT3		31
+#define GPI_SDIO0_CDATA_IN_BIT4		32
+#define GPI_SDIO0_CDATA_IN_BIT5		33
+#define GPI_SDIO0_CDATA_IN_BIT6		34
+#define GPI_SDIO0_CDATA_IN_BIT7		35
+#define GPI_SDIO1_CARD_DETECT_N		36
+#define GPI_SDIO1_CARD_WRITE_PRT	37
+#define GPI_SDIO1_CCMD_IN		38
+#define GPI_SDIO1_CDATA_IN_BIT0		39
+#define GPI_SDIO1_CDATA_IN_BIT1		40
+#define GPI_SDIO1_CDATA_IN_BIT2		41
+#define GPI_SDIO1_CDATA_IN_BIT3		42
+#define GPI_SDIO1_CDATA_IN_BIT4		43
+#define GPI_SDIO1_CDATA_IN_BIT5		44
+#define GPI_SDIO1_CDATA_IN_BIT6		45
+#define GPI_SDIO1_CDATA_IN_BIT7		46
+#define GPI_SPDIF_RX_SDIN		47
+#define GPI_SPI0_RXD			48
+#define GPI_SPI0_SS_IN_N		49
+#define GPI_SPI1_RXD			50
+#define GPI_SPI1_SS_IN_N		51
+#define GPI_SPI2_RXD			52
+#define GPI_SPI2_SS_IN_N		53
+#define GPI_SPI2AHB_RXD_BIT0		54
+#define GPI_SPI2AHB_RXD_BIT1		55
+#define GPI_SPI2AHB_RXD_BIT2		56
+#define GPI_SPI2AHB_RXD_BIT3		57
+#define GPI_SPI2AHB_SS_N		58
+#define GPI_SPI2AHB_SLV_SCLKIN		59
+#define GPI_SPI3_RXD			60
+#define GPI_SPI3_SS_IN_N		61
+#define GPI_UART0_CTSN			62
+#define GPI_UART0_DCDN			63
+#define GPI_UART0_DSRN			64
+#define GPI_UART0_RIN			65
+#define GPI_UART0_SIN			66
+#define GPI_UART1_SIN			67
+#define GPI_UART2_CTS_N			68
+#define GPI_UART2_DCD_N			69
+#define GPI_UART2_DSR_N			70
+#define GPI_UART2_RI_N			71
+#define GPI_UART2_SIN			72
+#define GPI_UART3_SIN			73
+#define GPI_USB_OVER_CURRENT		74
+
+
+#define PAD_GPIO_MAX			64
+
+//pins num rage(0-205) :PAD_GPIO(0~63) PAD_FUNC_SHARE(0~141)
+#define PAD_GPIO(num)			(num)
+#define PAD_FUNC_SHARE(num)		(PAD_GPIO_MAX + num)
+
+//pinmux
+#define GPIO(num)			(num & 0xFF)
+
+/* io pad control config */
+#define GPIO_DS(data)			((data << 0x0U) & 0xFU) /*driving strength[3:0]*/
+#define GPIO_PD(data)			((data << 0x4U) & 0x10U) /*pulldown enable[4]*/
+#define GPIO_PU(data)			((data << 0x5U) & 0x20U) /*pullup enable[5]*/
+#define GPIO_SMT(data)			((data << 0x6U) & 0x40U) /*schemit input enable[6]*/
+#define GPIO_IE(data)			((data << 0x7U) & 0x80U) /*input enable[7]*/
+#define GPIO_POS(data)			((data << 0x8U) & 0x100U) /*strength pullup enable[8]*/
+#define GPIO_SLEW(data)			((data << 0x9U) & 0xE00U) /*slew control[11:9]*/
+
+#define DO_REVERSE			(0x1)
+#define IO(config)			(config & 0xFFFF)
+#define DOUT(dout,reverse)		((dout & 0xFF) | (reverse << 31))
+#define DOEN(doen,reverse)		((doen & 0xFF) | (reverse << 31))
+#define DIN(din_reg)			(din_reg & 0xFF)
+
+
+#endif //_DT_BINDINGS_VIC7100_PINCTRL_STARFIVE_H
diff --git a/include/dt-bindings/starfive_fb.h b/include/dt-bindings/starfive_fb.h
new file mode 100644
index 000000000000..a7e014d61b29
--- /dev/null
+++ b/include/dt-bindings/starfive_fb.h
@@ -0,0 +1,47 @@
+#ifndef __STARFIVE_FB_H
+#define __STARFIVE_FB_H
+
+/*color code*/
+#define COLOR_CODE_16BIT_CONFIG1	0	//PACKET RGB565
+#define	COLOR_CODE_16BIT_CONFIG2	1	//UNPACKET RGB565
+#define	COLOR_CODE_16BIT_CONFIG3	2	//UNPACKET RGB565
+#define	COLOR_CODE_18BIT_CONFIG1	3	//PACKET RGB666
+#define	COLOR_CODE_18BIT_CONFIG2	4	//UNPACKET RGB666
+#define	COLOR_CODE_24BIT		5	//PACKET RGB888
+#define	COLOR_CODE_MAX			6
+
+/*command code*/
+#define	DCS_CMD				02
+#define	GEN_CMD				03
+#define	SW_PACK0			04
+#define	SW_PACK1			05
+#define	SW_PACK2			06
+#define	LW_PACK				07
+#define	SHUTDOWN_SW_PACK		08
+
+/*color format, need match to enum COLOR_FORMAT in starfive_vpp.h*/
+#define	COLOR_YUV422_UYVY	0
+#define	COLOR_YUV422_VYUY	1
+#define	COLOR_YUV422_YUYV	2
+#define	COLOR_YUV422_YVYU	3
+#define	COLOR_YUV420P	4
+#define	COLOR_YUV420_NV21	5
+#define	COLOR_YUV420_NV12	6
+#define	COLOR_RGB888_ARGB	7
+#define	COLOR_RGB888_ABGR	8
+#define	COLOR_RGB888_RGBA	9
+#define	COLOR_RGB888_BGRA	10
+#define	COLOR_RGB565	11
+
+#define SRC_COLORBAR_VIN_ISP  0
+#define SRC_DVP_SENSOR_VIN    1
+#define SRC_DVP_SENSOR_VIN_ISP 2
+#define SRC_CSI2RX_VIN_ISP    3
+#define SRC_DVP_SENSOR_VIN_OV5640 4
+
+#define    WIN_FMT_RGB565		4
+#define    WIN_FMT_xRGB1555		5
+#define    WIN_FMT_xRGB4444		6
+#define    WIN_FMT_xRGB8888		7
+
+#endif