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authorJoseph Lo <josephl@nvidia.com>2013-08-12 13:40:01 +0400
committerStephen Warren <swarren@nvidia.com>2013-08-12 22:22:39 +0400
commit444f9a8030ecda8dedd374fc3efed03d9f20e9cb (patch)
tree396cc998a2265b70ef00d80c2b88f4f62132fe56 /include/math-emu
parent5b795d051c61862cebf4f1d55edab6e9b3383b44 (diff)
downloadlinux-444f9a8030ecda8dedd374fc3efed03d9f20e9cb.tar.xz
ARM: tegra: config the polarity of the request of sys clock
When suspending to LP1 mode, the SYSCLK will be clock gated. And different board may have different polarity of the request of SYSCLK, this patch configure the polarity from the DT for the board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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