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| author | Tony Lindgren <tony@atomide.com> | 2019-06-10 14:48:05 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2019-06-10 14:52:22 +0300 |
| commit | 4e23be473e3063a9d3bc06bb0aee89885fffab0e (patch) | |
| tree | ba096852d21ac53b19f8dbdbdcff72dc009ee66c /include/linux/platform_data | |
| parent | b6a53c4c872ab6870eb455d10a6f7ff0d99b1b1f (diff) | |
| download | linux-4e23be473e3063a9d3bc06bb0aee89885fffab0e.tar.xz | |
bus: ti-sysc: Add support for module specific reset quirks
Some older interconnect target modules need module internal clock
toggling quirks to reset properly. We've been doing this in the
platform code earlier, but need to be able to it directly in the
ti-sysc driver when we no longer rely on on the platform code.
Let's add reset handling for 1-wire, i2c and watchdog. Later on
we can add more modules like msdi and dss as they get tested.
For dra7 pcie, we should be able to just use the rstctrl reset
driver when available.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/linux/platform_data')
| -rw-r--r-- | include/linux/platform_data/ti-sysc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 8822e99ff813..0c587d4fc718 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -47,6 +47,9 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_MODULE_QUIRK_HDQ1W BIT(17) +#define SYSC_MODULE_QUIRK_I2C BIT(16) +#define SYSC_MODULE_QUIRK_WDT BIT(15) #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14) #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) |