diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2023-12-22 01:03:39 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-12-23 01:53:49 +0300 |
| commit | 4d07a05397c8c15c37c8c3abb7afaea1dcd2f0e7 (patch) | |
| tree | 593e045747cbd9c3a4bc6babe33bb1b3a32f40f8 /include/linux/pci.h | |
| parent | 790815902ec61ba1715fd67d3cb9036e13c942bc (diff) | |
| download | linux-4d07a05397c8c15c37c8c3abb7afaea1dcd2f0e7.tar.xz | |
cxl: Calculate and store PCI link latency for the downstream ports
The latency is calculated by dividing the flit size over the bandwidth. Add
support to retrieve the flit size for the CXL switch device and calculate
the latency of the PCIe link. Cache the latency number with cxl_dport.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/pci.h')
| -rw-r--r-- | include/linux/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index dea043bc1e38..504a4ba2c29e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1364,6 +1364,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps); u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); +int pcie_link_speed_mbps(struct pci_dev *pdev); void pcie_print_link_status(struct pci_dev *dev); int pcie_reset_flr(struct pci_dev *dev, bool probe); int pcie_flr(struct pci_dev *dev); |