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| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-07 11:41:51 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-11 09:55:25 +0300 |
| commit | 39d1e3340c73e8f7eb1d6a8cae561c255ca7b1b0 (patch) | |
| tree | cf7b1d2ff233ab73dcaf019d21c2f4e61395b10d /include/linux/mtd | |
| parent | b24eaf5f23754cbfc80f3077440acaafc9551290 (diff) | |
| download | linux-39d1e3340c73e8f7eb1d6a8cae561c255ca7b1b0.tar.xz | |
mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
Make sure that when doing a lock() or an unlock() operation we don't clear
the QE bit from Status Register 2.
JESD216 revB or later offers information about the *default* Status
Register commands to use (see BFPT DWORDS[15], bits 22:20). In this
standard, Status Register 1 refers to the first data byte transferred on a
Read Status (05h) or Write Status (01h) command. Status register 2 refers
to the byte read using instruction 35h. Status register 2 is the second
byte transferred in a Write Status (01h) command.
Industry naming and definitions of these Status Registers may differ.
The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20.
There are cases in which writing only one byte to the Status Register 1
has the side-effect of clearing Status Register 2 and implicitly the Quad
Enable bit. This side-effect is hit just by the
BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1d736d3c8ab..d6ec55cc6d97 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -243,6 +243,9 @@ enum spi_nor_option_flags { SNOR_F_4B_OPCODES = BIT(6), SNOR_F_HAS_4BAIT = BIT(7), SNOR_F_HAS_LOCK = BIT(8), + SNOR_F_HAS_16BIT_SR = BIT(9), + SNOR_F_NO_READ_CR = BIT(10), + }; /** |