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| author | Jungseung Lee <js07.lee@samsung.com> | 2019-12-02 09:35:05 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-12-23 18:48:47 +0300 |
| commit | 52487e21689b40c8ce967ba97518b3dfaaa2d7b2 (patch) | |
| tree | aa76140c1cc26551acb7a662cf0c74f1a750d1a2 /include/linux/mtd/spi-nor.h | |
| parent | 01916e0443b9b46e34ad88696aadd1aab7ec142e (diff) | |
| download | linux-52487e21689b40c8ce967ba97518b3dfaaa2d7b2.tar.xz | |
mtd: spi-nor: Rename SR_TB to indicate the bit used
Each vendor uses different bits for SR_TB of flash.
To avoid ambiguity, rename SR_TB to indicate the bit used.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'include/linux/mtd/spi-nor.h')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 5a4623fc586b..5124c306f60b 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -128,7 +128,8 @@ #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ -#define SR_TB BIT(5) /* Top/Bottom protect */ +#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */ +#define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */ #define SR_SRWD BIT(7) /* SR write protect */ /* Spansion/Cypress specific status bits */ #define SR_E_ERR BIT(5) |