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| author | Marc Zyngier <maz@kernel.org> | 2020-03-04 23:33:12 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-03-20 20:48:21 +0300 |
| commit | 9058a4e980648e7d068a7f7726a8ea4c67d0e88a (patch) | |
| tree | 80a4e1431d39b6e0dcbcee6d9dad9f1b4c627a6b /include/linux/irqchip | |
| parent | b978c25f6ee7d4c79cbe918eed684e53887ec001 (diff) | |
| download | linux-9058a4e980648e7d068a7f7726a8ea4c67d0e88a.tar.xz | |
irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD
The GICv4.1 spec says that it is CONTRAINED UNPREDICTABLE to write to
any of the GICR_INV{LPI,ALL}R registers if GICR_SYNCR.Busy == 1.
To deal with it, we must ensure that only a single invalidation can
happen at a time for a given redistributor. Add a per-RD lock to that
effect and take it around the invalidation/syncr-read to deal with this.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200304203330.4967-6-maz@kernel.org
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c29a02678a6f..b28acfa71f82 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -652,6 +652,7 @@ struct rdists { struct { + raw_spinlock_t rd_lock; void __iomem *rd_base; struct page *pend_page; phys_addr_t phys_base; |