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| author | Marc Zyngier <maz@kernel.org> | 2019-12-24 14:10:38 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-01-22 17:22:21 +0300 |
| commit | f4a81f5a853e0b7c38bfad3afd6d0365d654e777 (patch) | |
| tree | 94a9ae3a3d67975fe81296e3a4d214e9cbd03e87 /include/linux/irqchip/arm-gic-v3.h | |
| parent | 3858d4dfdfb845e51ee8b4045f61ccba2c3111ee (diff) | |
| download | linux-f4a81f5a853e0b7c38bfad3afd6d0365d654e777.tar.xz | |
irqchip/gic-v4.1: Allow direct invalidation of VLPIs
Just like for INVALL, GICv4.1 has grown a VPE-aware INVLPI register.
Let's plumb it in and make use of the DirectLPI code in that case.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-16-maz@kernel.org
Diffstat (limited to 'include/linux/irqchip/arm-gic-v3.h')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 49ed6fa5e293..f0b8ca766e7d 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -247,6 +247,7 @@ #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) +#define GICR_INVLPIR_INTID GENMASK_ULL(31, 0) #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) #define GICR_INVLPIR_V GENMASK_ULL(63, 63) |