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| author | Joerg Roedel <jroedel@suse.de> | 2019-07-01 14:44:41 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-07-01 14:44:41 +0300 |
| commit | 39debdc1d7e615863b66e5e8c612e4f0e78b1e1b (patch) | |
| tree | 4a5a7e5b64524e88e73d19e4a96dc1cfecf8e967 /include/linux/iommu.h | |
| parent | 6fbc7275c7a9ba97877050335f290341a1fd8dbf (diff) | |
| parent | 9e6ea59f3ff37192fd7aec7821dca6ece629b7d0 (diff) | |
| download | linux-39debdc1d7e615863b66e5e8c612e4f0e78b1e1b.tar.xz | |
Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
Diffstat (limited to 'include/linux/iommu.h')
| -rw-r--r-- | include/linux/iommu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/iommu.h b/include/linux/iommu.h index e552c3b63f6f..86b4e0a75a97 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -29,6 +29,12 @@ * if the IOMMU page table format is equivalent. */ #define IOMMU_PRIV (1 << 5) +/* + * Non-coherent masters on few Qualcomm SoCs can use this page protection flag + * to set correct cacheability attributes to use an outer level of cache - + * last level cache, aka system cache. + */ +#define IOMMU_QCOM_SYS_CACHE (1 << 6) struct iommu_ops; struct iommu_group; |