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| author | David Woodhouse <David.Woodhouse@intel.com> | 2015-02-13 17:25:24 +0300 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2015-03-25 18:35:01 +0300 |
| commit | 44caf2f37f009b2affa743073fa935826b6ab2fd (patch) | |
| tree | 26cb22ee08041208b57a5dcd8b631205b99f3123 /include/linux/intel-iommu.h | |
| parent | bfa76d49576599a4b9f9b7a71f23d73d6dcff735 (diff) | |
| download | linux-44caf2f37f009b2affa743073fa935826b6ab2fd.tar.xz | |
iommu/vt-d: kill bogus ecap_niotlb_iunits()
As far back as I can see (which right now is a draft of the v1.2 spec
dating from September 2008), bits 24-31 of the Extended Capability Register
have already been reserved. I have no idea why anyone ever thought there
would be multiple sets of IOTLB registers, but we've never supported them
and all we do is make sure we map enough MMIO space for them.
Kill it dead. Those bits do actually have a different meaning now.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index a65208a8fe18..ee24ada20428 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -115,10 +115,8 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) * Extended Capability Register */ -#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) -#define ecap_max_iotlb_offset(e) \ - (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) +#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) #define ecap_coherent(e) ((e) & 0x1) #define ecap_qis(e) ((e) & 0x2) #define ecap_pass_through(e) ((e >> 6) & 0x1) |