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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-23 14:59:25 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-09-19 12:19:42 +0300 |
| commit | 362b334b17943d84d2878d2733f0ce695d45a2b6 (patch) | |
| tree | 4c66413c75bf8073061175a9bec046b12338a470 /include/linux/fsl | |
| parent | a7b8f48d2fa14330a1886f7fd640187c8b4470c5 (diff) | |
| download | linux-362b334b17943d84d2878d2733f0ce695d45a2b6.tar.xz | |
ARM: dts: r8a7791: Convert to new CPG/MSSR bindings
Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'include/linux/fsl')
0 files changed, 0 insertions, 0 deletions