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authorLen Brown <len.brown@intel.com>2005-08-30 01:02:17 +0400
committerLen Brown <len.brown@intel.com>2005-08-30 01:02:17 +0400
commit27a639a92d3289c4851105efcbc2f8b88969194f (patch)
tree09ee327d3ed3e2c40d5dc3b0f6b283477282deec /include/linux/8250_pci.h
parentd395bf12d1ba61437e546eb642f0d7ea666123ff (diff)
parentbf4e70e54cf31dcca48d279c7f7e71328eebe749 (diff)
downloadlinux-27a639a92d3289c4851105efcbc2f8b88969194f.tar.xz
Auto-update from upstream
Diffstat (limited to 'include/linux/8250_pci.h')
-rw-r--r--include/linux/8250_pci.h39
1 files changed, 37 insertions, 2 deletions
diff --git a/include/linux/8250_pci.h b/include/linux/8250_pci.h
index 5f3ab21b339b..3209dd46ea7d 100644
--- a/include/linux/8250_pci.h
+++ b/include/linux/8250_pci.h
@@ -1,2 +1,37 @@
-int pci_siig10x_fn(struct pci_dev *dev, int enable);
-int pci_siig20x_fn(struct pci_dev *dev, int enable);
+/*
+ * Definitions for PCI support.
+ */
+#define FL_BASE_MASK 0x0007
+#define FL_BASE0 0x0000
+#define FL_BASE1 0x0001
+#define FL_BASE2 0x0002
+#define FL_BASE3 0x0003
+#define FL_BASE4 0x0004
+#define FL_GET_BASE(x) (x & FL_BASE_MASK)
+
+/* Use successive BARs (PCI base address registers),
+ else use offset into some specified BAR */
+#define FL_BASE_BARS 0x0008
+
+/* do not assign an irq */
+#define FL_NOIRQ 0x0080
+
+/* Use the Base address register size to cap number of ports */
+#define FL_REGION_SZ_CAP 0x0100
+
+struct pciserial_board {
+ unsigned int flags;
+ unsigned int num_ports;
+ unsigned int base_baud;
+ unsigned int uart_offset;
+ unsigned int reg_shift;
+ unsigned int first_offset;
+};
+
+struct serial_private;
+
+struct serial_private *
+pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board);
+void pciserial_remove_ports(struct serial_private *priv);
+void pciserial_suspend_ports(struct serial_private *priv);
+void pciserial_resume_ports(struct serial_private *priv);