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authorOlof Johansson <olof@lixom.net>2019-04-28 22:50:38 +0300
committerOlof Johansson <olof@lixom.net>2019-04-28 22:50:38 +0300
commitb45da609a02460c6a34c395f03f891f1fb2a021a (patch)
tree13ec60794c74a4d35e193220a9299b1ad8aa4245 /include/dt-bindings
parent1e67323721f37f155f7b746c00e97432010769f8 (diff)
parente2c7f52bcdaf6ee24447cd7bc6100702c0b0f777 (diff)
downloadlinux-b45da609a02460c6a34c395f03f891f1fb2a021a.tar.xz
Merge tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT bindings update for 5.2: - Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems GmbH. - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610 SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10. - Update imx-scu bindings on resource table and general interrupt support. - Add bindings for i.MX MMDC memory controller. - Update i.MX7D ADC bindings to add missing '#io-channel-cells' property. * tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: iio: imx7d-adc: Add #io-channel-cells to required dt-bindings: arm: fsl: Add support for ZII i.MX7 RPU2 board dt-bindings: arm: fsl: Add devicetree binding for M53 Menlo board. dt-bindings: fsl: scu: add general interrupt support dt-bindings: arm: fsl: Add i.MX50 based boards dt-bindings: Add vendor prefix for Rakuten Kobo, Inc. dt-bindings: arm: add TQ boards dt-bindings: add vendor prefix for TQ Systems GmbH dt-bindings: arm: fsl: Add support for ZII VF610 SPB4 dt-bindings: arm: fsl: Add supported ZII VF610 boards to DT schema dt-bindings: arm: imx: Add the soc binding for imx8mm dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10 dt-bindings: memory-controllers: freescale: add MMDC binding doc of: Add vendor prefix for Menlo Systems GmbH bindings: fsl-imx-sdma: Document fsl,imx8mq-sdma compatbile string dt-bindings: firmware: imx-scu: add new resources to scu resource table dt-bindings: firmware: imx-scu: remove unused resources from scu resource table Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/firmware/imx/rsrc.h25
1 files changed, 8 insertions, 17 deletions
diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h
index 4481f2d60d65..4e61f6485097 100644
--- a/include/dt-bindings/firmware/imx/rsrc.h
+++ b/include/dt-bindings/firmware/imx/rsrc.h
@@ -36,15 +36,11 @@
#define IMX_SC_R_DC_0_BLIT1 20
#define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22
-#define IMX_SC_R_DC_0_CAPTURE0 23
-#define IMX_SC_R_DC_0_CAPTURE1 24
+#define IMX_SC_R_PERF 23
#define IMX_SC_R_DC_0_WARP 25
-#define IMX_SC_R_DC_0_INTEGRAL0 26
-#define IMX_SC_R_DC_0_INTEGRAL1 27
#define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30
-#define IMX_SC_R_DC_0_FRAC1 31
#define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34
@@ -53,17 +49,11 @@
#define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39
-#define IMX_SC_R_DC_1_CAPTURE0 40
-#define IMX_SC_R_DC_1_CAPTURE1 41
#define IMX_SC_R_DC_1_WARP 42
-#define IMX_SC_R_DC_1_INTEGRAL0 43
-#define IMX_SC_R_DC_1_INTEGRAL1 44
#define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47
-#define IMX_SC_R_DC_1_FRAC1 48
#define IMX_SC_R_DC_1 49
-#define IMX_SC_R_GPU_3_PID0 50
#define IMX_SC_R_DC_1_PLL_0 51
#define IMX_SC_R_DC_1_PLL_1 52
#define IMX_SC_R_SPI_0 53
@@ -303,8 +293,6 @@
#define IMX_SC_R_M4_0_UART 287
#define IMX_SC_R_M4_0_I2C 288
#define IMX_SC_R_M4_0_INTMUX 289
-#define IMX_SC_R_M4_0_SIM 290
-#define IMX_SC_R_M4_0_WDOG 291
#define IMX_SC_R_M4_0_MU_0B 292
#define IMX_SC_R_M4_0_MU_0A0 293
#define IMX_SC_R_M4_0_MU_0A1 294
@@ -323,8 +311,6 @@
#define IMX_SC_R_M4_1_UART 307
#define IMX_SC_R_M4_1_I2C 308
#define IMX_SC_R_M4_1_INTMUX 309
-#define IMX_SC_R_M4_1_SIM 310
-#define IMX_SC_R_M4_1_WDOG 311
#define IMX_SC_R_M4_1_MU_0B 312
#define IMX_SC_R_M4_1_MU_0A0 313
#define IMX_SC_R_M4_1_MU_0A1 314
@@ -337,7 +323,7 @@
#define IMX_SC_R_IRQSTR_SCU2 321
#define IMX_SC_R_IRQSTR_DSP 322
#define IMX_SC_R_ELCDIF_PLL 323
-#define IMX_SC_R_UNUSED6 324
+#define IMX_SC_R_OCRAM 324
#define IMX_SC_R_AUDIO_PLL_0 325
#define IMX_SC_R_PI_0 326
#define IMX_SC_R_PI_0_PWM_0 327
@@ -554,6 +540,11 @@
#define IMX_SC_R_VPU_MU_3 538
#define IMX_SC_R_VPU_ENC_1 539
#define IMX_SC_R_VPU 540
-#define IMX_SC_R_LAST 541
+#define IMX_SC_R_DMA_5_CH0 541
+#define IMX_SC_R_DMA_5_CH1 542
+#define IMX_SC_R_DMA_5_CH2 543
+#define IMX_SC_R_DMA_5_CH3 544
+#define IMX_SC_R_ATTESTATION 545
+#define IMX_SC_R_LAST 546
#endif /* __DT_BINDINGS_RSCRC_IMX_H */