Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...

1 files changed, 64 insertions, 0 deletions

diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+
+#define MMSS_SPDM_RESET			0
+#define MMSS_SPDM_RM_RESET		1
+#define VENUS0_RESET			2
+#define VPU_RESET			3
+#define MDSS_RESET			4
+#define AVSYNC_RESET			5
+#define CAMSS_PHY0_RESET		6
+#define CAMSS_PHY1_RESET		7
+#define CAMSS_PHY2_RESET		8
+#define CAMSS_CSI0_RESET		9
+#define CAMSS_CSI0PHY_RESET		10
+#define CAMSS_CSI0RDI_RESET		11
+#define CAMSS_CSI0PIX_RESET		12
+#define CAMSS_CSI1_RESET		13
+#define CAMSS_CSI1PHY_RESET		14
+#define CAMSS_CSI1RDI_RESET		15
+#define CAMSS_CSI1PIX_RESET		16
+#define CAMSS_CSI2_RESET		17
+#define CAMSS_CSI2PHY_RESET		18
+#define CAMSS_CSI2RDI_RESET		19
+#define CAMSS_CSI2PIX_RESET		20
+#define CAMSS_CSI3_RESET		21
+#define CAMSS_CSI3PHY_RESET		22
+#define CAMSS_CSI3RDI_RESET		23
+#define CAMSS_CSI3PIX_RESET		24
+#define CAMSS_ISPIF_RESET		25
+#define CAMSS_CCI_RESET			26
+#define CAMSS_MCLK0_RESET		27
+#define CAMSS_MCLK1_RESET		28
+#define CAMSS_MCLK2_RESET		29
+#define CAMSS_MCLK3_RESET		30
+#define CAMSS_GP0_RESET			31
+#define CAMSS_GP1_RESET			32
+#define CAMSS_TOP_RESET			33
+#define CAMSS_AHB_RESET			34
+#define CAMSS_MICRO_RESET		35
+#define CAMSS_JPEG_RESET		36
+#define CAMSS_VFE_RESET			37
+#define CAMSS_CSI_VFE0_RESET		38
+#define CAMSS_CSI_VFE1_RESET		39
+#define OXILI_RESET			40
+#define OXILICX_RESET			41
+#define OCMEMCX_RESET			42
+#define MMSS_RBCRP_RESET		43
+#define MMSSNOCAHB_RESET		44
+#define MMSSNOCAXI_RESET		45
+
+#endif