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| author | Stephen Boyd <sboyd@kernel.org> | 2022-03-09 21:47:28 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-03-09 21:47:28 +0300 |
| commit | 328212de9f846ad12b1330cf55bc5e04aac46cd0 (patch) | |
| tree | dfa6f5c919cf31217ac24eb41d2625ab309f54e0 /include/dt-bindings/clock | |
| parent | e783362eb54cd99b2cac8b3a9aeac942e6f6ac07 (diff) | |
| parent | 10b74af310735860510a533433b1d3ab2e05a138 (diff) | |
| download | linux-328212de9f846ad12b1330cf55bc5e04aac46cd0.tar.xz | |
Merge tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Improve the clocks for the rk3568 display outputs (parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on rk3568
- Reintroduce the expected fractional-divider behaviour that disappeared
with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
* tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: re-add rational best approximation algorithm to the fractional divider
clk/rockchip: Use of_device_get_match_data()
clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
clk: rockchip: Add more PLL rates for rk3568
Diffstat (limited to 'include/dt-bindings/clock')
0 files changed, 0 insertions, 0 deletions