diff options
| author | Andrew Victor <linux@maxim.org.za> | 2008-04-03 01:31:31 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-10 17:57:20 +0400 |
| commit | 32b1216d1e338d69cc5a11ca81fc247eb8ddfb2e (patch) | |
| tree | 0196e474c2513353e627122a1a4c77c99bcb9fec /include/asm-arm | |
| parent | c21098ea5608c98b5ada1b7ec82522c7c53869eb (diff) | |
| download | linux-32b1216d1e338d69cc5a11ca81fc247eb8ddfb2e.tar.xz | |
[ARM] 4913/1: [AT91] PMC_MDIV definitions
The allowed values for the MDIV field (Master Clock Division) in the
PMC controller differ between the AT91RM9200 and AT91SAM9/CAP9.
To remove possible confusion, change the definitions to be more explicit.
Also define the Processor Clock Division bits.
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 52cd8e5dabc9..c2b13c280155 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -76,10 +76,17 @@ #define AT91_PMC_PRES_32 (5 << 2) #define AT91_PMC_PRES_64 (6 << 2) #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91_PMC_MDIV_1 (0 << 8) -#define AT91_PMC_MDIV_2 (1 << 8) -#define AT91_PMC_MDIV_3 (2 << 8) -#define AT91_PMC_MDIV_4 (3 << 8) +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ |