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| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-10 22:54:46 +0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-17 04:32:27 +0400 |
| commit | d75d538899da00bdf8f152c65a99eda1ab59daa3 (patch) | |
| tree | ac90e2118786afbc380968f56c22f0b2cd27af58 /fs/ufs/super.c | |
| parent | 9cc2570a1dd74c22b4644b325257cf92d4cdb031 (diff) | |
| download | linux-d75d538899da00bdf8f152c65a99eda1ab59daa3.tar.xz | |
[media] r820t: proper initialize the PLL register
The rtl-sdr library, from where this driver was initially
based, doesn't use half PLL clock, but this is used on
the Realtek Kernel driver. So, also do the same here.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Tested-by: Antti Palosaari <crope@iki.fi>
Diffstat (limited to 'fs/ufs/super.c')
0 files changed, 0 insertions, 0 deletions