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authorMike Frysinger <michael.frysinger@analog.com>2007-11-21 11:08:58 +0300
committerBryan Wu <bryan.wu@analog.com>2007-11-21 11:08:58 +0300
commit9e83b98a79d25136282a1757f879c40ee929a28b (patch)
tree1ec7588320b7e95f05eab8b2f9a06c07f48034bc /fs/anon_inodes.c
parentb5f87aa41db4d5cd64ca77f10b33fdfba61a47d7 (diff)
downloadlinux-9e83b98a79d25136282a1757f879c40ee929a28b.tar.xz
Blackfin arch: add support for working around anomaly 05000312
Anomaly 05000312 - Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted: DESCRIPTION: When instruction cache is enabled, erroneous behavior may occur when any of the following instructions are interrupted: . CSYNC • SSYNC • LCx = • LTx = (only when LCx is non-zero) • LBx = (only when LCx is non-zero) When this problem occurs, a variety of incorrect things could happen, including an illegal instruction exception. Additional errors could show up as an exception, a hardware error, or an instruction that is valid but different than the one that was expected. WORKAROUND: Place a cli before all SSYNC, CSYNC, "LCx =", "LTx =", and "LBx =" instructions to disable interrupts, and place an sti after each of these instructions to re-enable interrupts. When these instructions are executed in code that is already non-interruptible, the problem will not occur. Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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