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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-05-07 18:38:08 +0300
committerVinod Koul <vinod.koul@intel.com>2015-05-18 08:29:34 +0300
commitee0fe35c8dcde29e7f65c34c286378750c075bf3 (patch)
tree305667bc33318b5f44e1bb68057188d4d40be8de /drivers
parent5ebe6afaf0057ac3eaeb98defd5456894b446d22 (diff)
downloadlinux-ee0fe35c8dcde29e7f65c34c286378750c075bf3.tar.xz
dmaengine: xdmac: Handle descriptor's view 3 registers
The XDMAC DMA controller uses a concept of views to be able to handle descriptors of different sizes. So far, only the views 1 and 2 were handled by the driver. Unfortunately, we need some of the configuration fields found in the view 3 in order to support memset and interleaved transfers. Add the definition for the view 3 registers, and the needed code to handle view 3 descriptors. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/dma/at_xdmac.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 933e4b338459..2d039512ecb3 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -236,6 +236,10 @@ struct at_xdmac_lld {
dma_addr_t mbr_sa; /* Source Address Member */
dma_addr_t mbr_da; /* Destination Address Member */
u32 mbr_cfg; /* Configuration Register */
+ u32 mbr_bc; /* Block Control Register */
+ u32 mbr_ds; /* Data Stride Register */
+ u32 mbr_sus; /* Source Microblock Stride Register */
+ u32 mbr_dus; /* Destination Microblock Stride Register */
};
@@ -359,6 +363,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
if (at_xdmac_chan_is_cyclic(atchan)) {
reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
+ } else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) {
+ reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
} else {
/*
* No need to write AT_XDMAC_CC reg, it will be done when the