diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2019-06-21 09:15:14 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-06-21 17:50:10 +0300 |
| commit | 36e92f611e33d5e00849d175805fc6c6d4332c25 (patch) | |
| tree | c1bde8c7c18eace17a328830f2eaee4e319845cf /drivers | |
| parent | f5a3cb90b802da2dee8bc1dc39339b6521c33652 (diff) | |
| download | linux-36e92f611e33d5e00849d175805fc6c6d4332c25.tar.xz | |
staging: mt7621-pci: disable pcie port clock if there is no pcie link
When there is no pcie link detected we have to properly disable the
port pcie clock.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index de09bda0b4cd..f6b91b29fb9c 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -45,6 +45,7 @@ #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) /* rt_sysc_membase relative registers */ +#define RALINK_CLKCFG1 0x30 #define RALINK_PCIE_CLK_GEN 0x7c #define RALINK_PCIE_CLK_GEN1 0x80 @@ -221,6 +222,11 @@ static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port) return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0; } +static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port) +{ + rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1); +} + static inline void mt7621_control_assert(struct mt7621_pcie_port *port) { u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID); @@ -475,6 +481,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie) slot); phy_power_off(port->phy); mt7621_control_assert(port); + mt7621_pcie_port_clk_disable(port); port->enabled = false; } } |