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| author | kartik <kkartik@nvidia.com> | 2021-12-06 14:52:45 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-02-24 19:09:13 +0300 |
| commit | 6f259bf1619bbff6118c1e556044c0cb4020bbb6 (patch) | |
| tree | 37de41a980090dc4d121c6efb5e4cff823e7bad0 /drivers | |
| parent | 1e5cf1452eb0f17b6bd6d51786c7b39ba175f340 (diff) | |
| download | linux-6f259bf1619bbff6118c1e556044c0cb4020bbb6.tar.xz | |
soc/tegra: fuse: Update nvmem cell list
Update tegra_fuse_cells with below entries:
- gcplex-config-fuse:
Configuration bits for GPU, used to enable/disable write protected
region used for storing GPU firmware.
- pdi0:
Unique per chip public identifier.
- pdi1:
Unique per chip public identifier.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/soc/tegra/fuse/fuse-tegra.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 913103ee5432..10d2ae99babd 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved. */ #include <linux/clk.h> @@ -162,6 +162,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bit_offset = 0, .nbits = 32, }, { + .name = "gcplex-config-fuse", + .offset = 0x1c8, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { .name = "tsensor-realignment", .offset = 0x1fc, .bytes = 4, @@ -179,6 +185,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bytes = 4, .bit_offset = 0, .nbits = 32, + }, { + .name = "pdi0", + .offset = 0x300, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "pdi1", + .offset = 0x304, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, }, }; |