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| author | andy.hu <andy.hu@starfivetech.com> | 2024-06-21 12:24:22 +0300 |
|---|---|---|
| committer | andy.hu <andy.hu@starfivetech.com> | 2024-06-21 12:24:22 +0300 |
| commit | ea9fba1d65c5662765794491b93b63cbbf033bc0 (patch) | |
| tree | 44409c3dba72e14dd2900978aa46803f60e9346a /drivers | |
| parent | fc06d5568eece0a809106fb6b8a081e2967ef2b6 (diff) | |
| parent | 9c97134b63f6214d6bb2f76d754079f2b1a9a290 (diff) | |
| download | linux-ea9fba1d65c5662765794491b93b63cbbf033bc0.tar.xz | |
Merge branch 'CR_11297_ethernet_phy_6.6_hal.feng' into 'jh7110-6.6.y-devel'
CR_11297_ethernet_phy_6.6_hal.feng
See merge request sdk/linux!1063
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/motorcomm.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 7a11fdb687cc..6bc3333b76dc 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -792,7 +792,7 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) { int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; - u32 rx_reg, tx_reg; + u32 rx_reg, tx_reg, tx_fe_reg; u16 mask, val = 0; int ret; @@ -804,6 +804,10 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) ytphy_rgmii_delays, tb_size, NULL, YT8521_RC1R_RGMII_1_950_NS); + tx_fe_reg = ytphy_get_delay_reg_value(phydev, "tx-fe-internal-delay-ps", + ytphy_rgmii_delays, tb_size, NULL, + YT8521_RC1R_RGMII_0_000_NS); + switch (phydev->interface) { case PHY_INTERFACE_MODE_RGMII: rxc_dly_en = 0; @@ -813,11 +817,13 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) break; case PHY_INTERFACE_MODE_RGMII_TXID: rxc_dly_en = 0; - val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); + val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg) | + FIELD_PREP(YT8521_RC1R_FE_TX_DELAY_MASK, tx_fe_reg); break; case PHY_INTERFACE_MODE_RGMII_ID: val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | - FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); + FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg) | + FIELD_PREP(YT8521_RC1R_FE_TX_DELAY_MASK, tx_fe_reg); break; default: /* do not support other modes */ return -EOPNOTSUPP; @@ -828,8 +834,9 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) if (ret < 0) return ret; + mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK | /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ - mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; + YT8521_RC1R_FE_TX_DELAY_MASK; return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); } |