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| author | Andrew Jeffery <andrew@aj.id.au> | 2017-09-20 08:30:17 +0300 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2017-12-28 22:44:48 +0300 |
| commit | 9f3e13c74e1b4f370c3de06cb504c003091c9673 (patch) | |
| tree | fbd78134e88a095eb1e8667a3dbe2e55388bb7d9 /drivers/watchdog/aspeed_wdt.c | |
| parent | be17980d9be5a5c1ece83836b24fabce648b92aa (diff) | |
| download | linux-9f3e13c74e1b4f370c3de06cb504c003091c9673.tar.xz | |
watchdog: aspeed: Retain watchdog enabled state
An unintended post-condition of probe() is that the watchdog is
disabled. This behaviour was introduced by an unnecessary write to the
control register to configure the hardware based on the devicetree. The
write is unnecessary because the cached control value that is
manipulated by the code parsing the devicetree is eventually written by
aspeed_wdt_enable(), which is when we care how the control register
should be configured.
Remove the write to restore expected behaviour.
Fixes: b7f0b8ad25f3 ("drivers/watchdog: ASPEED reference dev tree properties for config")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog/aspeed_wdt.c')
| -rw-r--r-- | drivers/watchdog/aspeed_wdt.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index 79cc766cd30f..6c6dd3f4c48d 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -243,9 +243,13 @@ static int aspeed_wdt_probe(struct platform_device *pdev) if (of_property_read_bool(np, "aspeed,external-signal")) wdt->ctrl |= WDT_CTRL_WDT_EXT; - writel(wdt->ctrl, wdt->base + WDT_CTRL); - if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { + /* + * The watchdog is running, but invoke aspeed_wdt_start() to + * write wdt->ctrl to WDT_CTRL to ensure the watchdog's + * configuration conforms to the driver's expectations. + * Primarily, ensure we're using the 1MHz clock source. + */ aspeed_wdt_start(&wdt->wdd); set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); } |