diff options
| author | Chris Brandt <chris.brandt@renesas.com> | 2019-05-15 18:20:42 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-05-21 11:25:59 +0300 |
| commit | 2195e3af9079ea067079e98446ea6a457c81a98c (patch) | |
| tree | 93cef59657f35102c5051d54ee3bd0f9ac74a90a /drivers/usb/renesas_usbhs | |
| parent | 97a7968448cb0ef5c15e3d395746b108b1a55556 (diff) | |
| download | linux-2195e3af9079ea067079e98446ea6a457c81a98c.tar.xz | |
usb: renesas_usbhs: add support for CNEN bit
For some SoC, CNEN must be set for USB Device mode operation.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/renesas_usbhs')
| -rw-r--r-- | drivers/usb/renesas_usbhs/common.c | 6 | ||||
| -rw-r--r-- | drivers/usb/renesas_usbhs/common.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c index 1de7a44f3415..734fb4e542c5 100644 --- a/drivers/usb/renesas_usbhs/common.c +++ b/drivers/usb/renesas_usbhs/common.c @@ -114,6 +114,12 @@ void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable) u16 mask = DCFM | DRPD | DPRPU | HSE | USBE; u16 val = HSE | USBE; + /* CNEN bit is required for function operation */ + if (usbhs_get_dparam(priv, has_cnen)) { + mask |= CNEN; + val |= CNEN; + } + /* * if enable * diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h index 1fbffb7bbc8f..de74ebd1a347 100644 --- a/drivers/usb/renesas_usbhs/common.h +++ b/drivers/usb/renesas_usbhs/common.h @@ -104,6 +104,7 @@ struct usbhs_priv; /* SYSCFG */ #define SCKE (1 << 10) /* USB Module Clock Enable */ +#define CNEN (1 << 8) /* Single-ended receiver operation Enable */ #define HSE (1 << 7) /* High-Speed Operation Enable */ #define DCFM (1 << 6) /* Controller Function Select */ #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ |