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authorDinh Nguyen <dinguyen@kernel.org>2017-11-01 18:34:53 +0300
committerFelipe Balbi <felipe.balbi@linux.intel.com>2017-12-12 14:04:22 +0300
commitf2830ad455ec0fdc386baeb9d654f7095bf849da (patch)
tree36e4ec9685c427897027408661f9f5d338c2c939 /drivers/usb/dwc2
parent5785e87a3db80a033c16e19de7741bc444f50f1a (diff)
downloadlinux-f2830ad455ec0fdc386baeb9d654f7095bf849da.tar.xz
usb: dwc2: add optional usb ecc reset bit
The dwc2 USB controller in Stratix10 has an additional ECC reset bit that needs to get de-asserted in order for the controller to work properly. Acked-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc2')
-rw-r--r--drivers/usb/dwc2/core.h1
-rw-r--r--drivers/usb/dwc2/platform.c10
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index f66c94130cac..f22f2e9d0759 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -925,6 +925,7 @@ struct dwc2_hsotg {
int irq;
struct clk *clk;
struct reset_control *reset;
+ struct reset_control *reset_ecc;
unsigned int queuing_high_bandwidth:1;
unsigned int srp_success:1;
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 3e26550d13dd..4703478f702f 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -221,6 +221,15 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
reset_control_deassert(hsotg->reset);
+ hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
+ if (IS_ERR(hsotg->reset_ecc)) {
+ ret = PTR_ERR(hsotg->reset_ecc);
+ dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
+ return ret;
+ }
+
+ reset_control_deassert(hsotg->reset_ecc);
+
/* Set default UTMI width */
hsotg->phyif = GUSBCFG_PHYIF16;
@@ -319,6 +328,7 @@ static int dwc2_driver_remove(struct platform_device *dev)
dwc2_lowlevel_hw_disable(hsotg);
reset_control_assert(hsotg->reset);
+ reset_control_assert(hsotg->reset_ecc);
return 0;
}