diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2019-03-22 16:16:53 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2019-11-02 12:13:31 +0300 |
| commit | 7bffd97eb7ab8a67de718bdd626e9fad27ee61b9 (patch) | |
| tree | 7ab66d6055d200507e2dbb80ffaebfb1d6229cca /drivers/thunderbolt/tb.c | |
| parent | 17a8f815a0df1e164979222ba7ab796b294c1748 (diff) | |
| download | linux-7bffd97eb7ab8a67de718bdd626e9fad27ee61b9.tar.xz | |
thunderbolt: Add downstream PCIe port mappings for Alpine and Titan Ridge
In order to keep PCIe hierarchies consistent across hotplugs, add
hard-coded PCIe downstream port to Thunderbolt port for Alpine Ridge and
Titan Ridge as well.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tb.c')
| -rw-r--r-- | drivers/thunderbolt/tb.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index e8e2d20cf4c6..c24b577e049e 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -342,10 +342,13 @@ static struct tb_port *tb_find_pcie_down(struct tb_switch *sw, * Hard-coded Thunderbolt port to PCIe down port mapping * per controller. */ - if (tb_switch_is_cactus_ridge(sw)) + if (tb_switch_is_cactus_ridge(sw) || + tb_switch_is_alpine_ridge(sw)) index = !phy_port ? 6 : 7; else if (tb_switch_is_falcon_ridge(sw)) index = !phy_port ? 6 : 8; + else if (tb_switch_is_titan_ridge(sw)) + index = !phy_port ? 8 : 9; else goto out; |