diff options
| author | Wei Ni <wni@nvidia.com> | 2016-03-29 13:29:15 +0300 |
|---|---|---|
| committer | Eduardo Valentin <edubezval@gmail.com> | 2016-05-17 17:28:28 +0300 |
| commit | 8204104f3598b6f29a8858df16c15c156014b863 (patch) | |
| tree | 8df5caa5f46e45ac44c142e053204ddb87a3e09d /drivers/thermal/tegra/soctherm-fuse.c | |
| parent | 65b6d57c24ed0aff1fc571e42d8f51bdfcce9a8e (diff) | |
| download | linux-8204104f3598b6f29a8858df16c15c156014b863.tar.xz | |
thermal: tegra: add Tegra210 specific SOC_THERM driver
Add Tegra210 specific SOC_THERM driver.
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'drivers/thermal/tegra/soctherm-fuse.c')
| -rw-r--r-- | drivers/thermal/tegra/soctherm-fuse.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c index 931c299ab0e8..29963180c453 100644 --- a/drivers/thermal/tegra/soctherm-fuse.c +++ b/drivers/thermal/tegra/soctherm-fuse.c @@ -28,7 +28,18 @@ #define FUSE_TSENSOR_COMMON 0x180 /* + * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON: + * 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * * Tegra12x, etc: + * In chips prior to Tegra210, this fuse was incorrectly sized as 26 bits, + * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits + * were obtained via the FUSE_SPARE_REALIGNMENT_REG register [5:0]. + * * FUSE_TSENSOR_COMMON: * 3 2 1 0 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |