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authorShawn Lin <shawn.lin@rock-chips.com>2018-03-21 05:39:19 +0300
committerHeiko Stuebner <heiko@sntech.de>2018-03-23 10:49:35 +0300
commit4b0556a441dd37e598887215bc89b49a6ef525b3 (patch)
tree683baf2164de1a4b82fafcd8eefdf90995de704c /drivers/tee
parent4ee3fd4abeca30d530fe67972f1964f7454259d6 (diff)
downloadlinux-4b0556a441dd37e598887215bc89b49a6ef525b3.tar.xz
clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228
commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") catches one gremlin again for clk-rk3228.c that the parent of SDMMC phase clock should be sclk_sdmmc0, but not sclk_sdmmc. However, the naming of the sdmmc clocks varies in the manual with the card clock having the 0 while the hclk is named without appended 0. So standardize one one format to prevent confusion, as there also is only one (non-sdio) mmc controller on the soc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/tee')
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