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authorMichael Welling <mwelling@ieee.org>2015-05-24 05:13:43 +0300
committerMark Brown <broonie@kernel.org>2015-05-25 15:00:04 +0300
commit4373f8b6dab0de16e5ecf527626d958d20a45b3b (patch)
tree8cd6e6955a7ebb50ac2c5075da8a73f5a3fc291d /drivers/spi
parentbe632f658462f5c80817a383c6d9b9790c0e7d1f (diff)
downloadlinux-4373f8b6dab0de16e5ecf527626d958d20a45b3b.tar.xz
spi: omap2-mcspi: Fix set_cs function for active high
The core spi driver swaps the polarity of the enable based on SPI_CS_HIGH. The omap2 controller has an internal configuration register bit called OMAP2_MCSPI_CHCONF_EPOL to handle active high chip selects as well. So we have to revert swap the polarity back for the correct setting of the OMAP2_MCSPI_CHCONF_FORCE bit in omap2_mcspi_set_cs. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-omap2-mcspi.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 304b427db95d..502db29fd0fe 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -247,6 +247,13 @@ static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
{
u32 l;
+ /* The controller handles the inverted chip selects
+ * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
+ * the inversion from the core spi_set_cs function.
+ */
+ if (spi->mode & SPI_CS_HIGH)
+ enable = !enable;
+
if (spi->controller_state) {
l = mcspi_cached_chconf0(spi);