diff options
| author | Dilip Kota <eswara.kota@linux.intel.com> | 2020-07-17 09:27:53 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-07-22 03:55:56 +0300 |
| commit | 94eca904cb97f9cfa90e3e558fb73c49d2e42f91 (patch) | |
| tree | 9b0eb0f3b701f291e9a8091e4cf2cf46f4920791 /drivers/spi | |
| parent | 8d19d665e0aca28c4bd8a024241b05f74841a315 (diff) | |
| download | linux-94eca904cb97f9cfa90e3e558fb73c49d2e42f91.tar.xz | |
spi: lantiq: Add support to acknowledge interrupt
On newer chipsets interrupt need to be acknowledged as they use
different interrupt controller which does not acknowledge the
interrupts automatically.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/608923b484d9ef239b44bb545c0b79b27030a6ae.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-lantiq-ssc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c index 78c6b131d069..aa984e704b05 100644 --- a/drivers/spi/spi-lantiq-ssc.c +++ b/drivers/spi/spi-lantiq-ssc.c @@ -160,6 +160,7 @@ struct lantiq_ssc_hwcfg { unsigned int irnen_t; unsigned int irncr; unsigned int irnicr; + bool irq_ack; }; struct lantiq_ssc_spi { @@ -622,9 +623,14 @@ static void rx_request(struct lantiq_ssc_spi *spi) static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) { struct lantiq_ssc_spi *spi = data; + const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; + u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); unsigned long flags; spin_lock_irqsave(&spi->lock, flags); + if (hwcfg->irq_ack) + lantiq_ssc_writel(spi, val, hwcfg->irncr); + if (spi->tx) { if (spi->rx && spi->rx_todo) rx_fifo_read_full_duplex(spi); @@ -659,13 +665,18 @@ completed: static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) { struct lantiq_ssc_spi *spi = data; + const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); + u32 val = lantiq_ssc_readl(spi, hwcfg->irncr); unsigned long flags; if (!(stat & LTQ_SPI_STAT_ERRORS)) return IRQ_NONE; spin_lock_irqsave(&spi->lock, flags); + if (hwcfg->irq_ack) + lantiq_ssc_writel(spi, val, hwcfg->irncr); + if (stat & LTQ_SPI_STAT_RUE) dev_err(spi->dev, "receive underflow error\n"); if (stat & LTQ_SPI_STAT_TUE) @@ -796,6 +807,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { .irnen_t = LTQ_SPI_IRNEN_T_XWAY, .irnicr = 0xF8, .irncr = 0xFC, + .irq_ack = false, }; static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { @@ -803,6 +815,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { .irnen_t = LTQ_SPI_IRNEN_T_XRX, .irnicr = 0xF8, .irncr = 0xFC, + .irq_ack = false, }; static const struct of_device_id lantiq_ssc_match[] = { |