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authorHuacai Chen <chenhc@lemote.com>2014-03-22 13:21:44 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 12:16:53 +0400
commitc14af233fbe279d0e561ecf84f1208b1bae087ef (patch)
tree2e4beb6ddeb749cc49cfcb433006fce5ad8e7364 /drivers/spi/spi-fsl-dspi.c
parent61d3edb862716c4ab8d7d7fec48101b4d35e9e52 (diff)
downloadlinux-c14af233fbe279d0e561ecf84f1208b1bae087ef.tar.xz
MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()
The original MIPS hibernate code flushes cache and TLB entries in swsusp_arch_resume(). But they are removed in Commit 44eeab67416711 (MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross- CPU flush is surely unnecessary because all but the local CPU have already been disabled. But a local flush (at least the TLB flush) is needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is very easy to produce a kernel panic (kernel page fault, or unaligned access). The root cause is E1000E driver use vzalloc_node() to allocate pages, the stale TLB entries of the booting kernel will be misused by the resumed target kernel. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6643/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/spi/spi-fsl-dspi.c')
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