diff options
| author | Uma Krishnan <ukrishn@linux.vnet.ibm.com> | 2018-03-26 19:34:42 +0300 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2018-04-19 02:32:50 +0300 |
| commit | 23239eeccbe647b1da60dd930931c9520a336749 (patch) | |
| tree | f50e89f5fa1d2856393e9deb02144b72d91d9a54 /drivers/scsi/cxlflash/superpipe.c | |
| parent | 402a55ea473a37b06eeae9abda00886bfd3bfe6d (diff) | |
| download | linux-23239eeccbe647b1da60dd930931c9520a336749.tar.xz | |
scsi: cxlflash: Setup LISNs for user contexts
The SISLite specification has been updated for OCXL to support communicating
data to generate AFU interrupts to the AFU. This includes a new capability bit
that is advertised for OCXL AFUs and new registers to hold the object handle
and translation PASID of each interrupt. For Power, the object handle is the
mapped trigger page. Note that because these mappings are kernel only, the
PASID of a kernel context must be used to satisfy the translation.
Signed-off-by: Uma Krishnan <ukrishn@linux.vnet.ibm.com>
Acked-by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/cxlflash/superpipe.c')
| -rw-r--r-- | drivers/scsi/cxlflash/superpipe.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/scsi/cxlflash/superpipe.c b/drivers/scsi/cxlflash/superpipe.c index 2fe79df5c73c..04a3bf9dc85f 100644 --- a/drivers/scsi/cxlflash/superpipe.c +++ b/drivers/scsi/cxlflash/superpipe.c @@ -269,6 +269,7 @@ static int afu_attach(struct cxlflash_cfg *cfg, struct ctx_info *ctxi) int rc = 0; struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ); u64 val; + int i; /* Unlock cap and restrict user to read/write cmds in translated mode */ readq_be(&ctrl_map->mbox_r); @@ -282,6 +283,19 @@ static int afu_attach(struct cxlflash_cfg *cfg, struct ctx_info *ctxi) goto out; } + if (afu_is_ocxl_lisn(afu)) { + /* Set up the LISN effective address for each interrupt */ + for (i = 0; i < ctxi->irqs; i++) { + val = cfg->ops->get_irq_objhndl(ctxi->ctx, i); + writeq_be(val, &ctrl_map->lisn_ea[i]); + } + + /* Use primary HWQ PASID as identifier for all interrupts */ + val = hwq->ctx_hndl; + writeq_be(SISL_LISN_PASID(val, val), &ctrl_map->lisn_pasid[0]); + writeq_be(SISL_LISN_PASID(0UL, val), &ctrl_map->lisn_pasid[1]); + } + /* Set up MMIO registers pointing to the RHT */ writeq_be((u64)ctxi->rht_start, &ctrl_map->rht_start); val = SISL_RHT_CNT_ID((u64)MAX_RHT_PER_CONTEXT, (u64)(hwq->ctx_hndl)); |