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authorMatthew R. Ochs <mrochs@linux.vnet.ibm.com>2017-06-22 05:16:33 +0300
committerMartin K. Petersen <martin.petersen@oracle.com>2017-06-26 22:01:13 +0300
commit3223c01aa1cec60d59bd218aca5e202b558d225a (patch)
treee00bfee5a8984b6ff929564eacfc2aaaa4da509d /drivers/scsi/cxlflash/sislite.h
parentbc88ac47d5cb11c7dd9896781f793fae519d53fa (diff)
downloadlinux-3223c01aa1cec60d59bd218aca5e202b558d225a.tar.xz
scsi: cxlflash: Support WS16 unmap
The cxlflash driver supports performing a write-same16 to scrub virtual luns when they are released by a user. To date, AFUs for adapters that are supported by cxlflash do not have the capability to unmap as part of the WS operation. This can lead to fragmented flash devices which results in performance degradation. Future AFUs can optionally support unmap write-same commands and reflects this support via the context control register. This provides userspace applications with direct visibility such that they need not depend on a host API. Detect unmap support during cxlflash initialization by reading the context control register associated with the primary hardware queue. Update the existing write_same16() routine to set the unmap bit in the CDB when unmap is supported by the host. Signed-off-by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com> Signed-off-by: Uma Krishnan <ukrishn@linux.vnet.ibm.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/cxlflash/sislite.h')
-rw-r--r--drivers/scsi/cxlflash/sislite.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/scsi/cxlflash/sislite.h b/drivers/scsi/cxlflash/sislite.h
index d671fae19697..09daa86670fc 100644
--- a/drivers/scsi/cxlflash/sislite.h
+++ b/drivers/scsi/cxlflash/sislite.h
@@ -283,6 +283,7 @@ struct sisl_host_map {
__be64 rrq_end; /* write sequence: start followed by end */
__be64 cmd_room;
__be64 ctx_ctrl; /* least significant byte or b56:63 is LISN# */
+#define SISL_CTX_CTRL_UNMAP_SECTOR 0x8000000000000000ULL /* b0 */
__be64 mbox_w; /* restricted use */
__be64 sq_start; /* Submission Queue (R/W): write sequence and */
__be64 sq_end; /* inclusion semantics are the same as RRQ */