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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2022-11-17 14:08:06 +0300
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>2022-11-22 21:34:02 +0300
commiteb78d3604d6bcbe9743e036114c33a5a17090a0a (patch)
treeb746613a53d2a6b40a44105aae0fec6659f9deb9 /drivers/pinctrl
parentf0f31de35644537a18059dac0e4a06f8b1c1c6c0 (diff)
downloadlinux-eb78d3604d6bcbe9743e036114c33a5a17090a0a.tar.xz
pinctrl: intel: Enumerate PWM device when community has a capability
Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 52ecd66ce357..d74c8b650aa7 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -21,6 +21,8 @@
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_data/x86/pwm-lpss.h>
+
#include "../core.h"
#include "pinctrl-intel.h"
@@ -46,6 +48,8 @@
#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
+#define PWMC 0x204
+
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
@@ -1499,6 +1503,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}
+static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
+ struct intel_community *community)
+{
+ static const struct pwm_lpss_boardinfo info = {
+ .clk_rate = 19200000,
+ .npwm = 1,
+ .base_unit_bits = 22,
+ .bypass = true,
+ };
+ struct pwm_lpss_chip *pwm;
+
+ if (!(community->features & PINCTRL_FEATURE_PWM))
+ return 0;
+
+ if (!IS_REACHABLE(CONFIG_PWM_LPSS))
+ return 0;
+
+ pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
+ return PTR_ERR_OR_ZERO(pwm);
+}
+
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
@@ -1584,6 +1609,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
if (ret)
return ret;
+
+ ret = intel_pinctrl_probe_pwm(pctrl, community);
+ if (ret)
+ return ret;
}
irq = platform_get_irq(pdev, 0);