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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-31 11:05:13 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-05-31 13:42:04 +0300 |
| commit | 9eaa98a63c8a34a807ba95e384aacd28fa60ddd9 (patch) | |
| tree | 96aec0f81f4f6208ff08c1580429724dbd5542d1 /drivers/pinctrl/uniphier/pinctrl-uniphier.h | |
| parent | fc78a56631d13901dd8bac5efb46e8fdcd89976b (diff) | |
| download | linux-9eaa98a63c8a34a807ba95e384aacd28fa60ddd9.tar.xz | |
pinctrl: uniphier: rename macros for drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Some of the configuration registers on it have
3-bit width.
The feature will be supported in the next commit, but a problem is
that macro names are getting longer and longer in the current naming
scheme.
Before moving forward, this commit renames macros as follows:
UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT
UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT
UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4
UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5
UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier/pinctrl-uniphier.h')
| -rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 032241300aca..7f3e7ffe0096 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -41,16 +41,16 @@ struct platform_device; #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \ - 1) -/* supported drive strength (mA) */ -#define UNIPHIER_PIN_DRV_STR_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \ +/* drive control type */ +#define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \ (UNIPHIER_PIN_DRVCTRL_BITS)) -#define UNIPHIER_PIN_DRV_STR_BITS 3 -#define UNIPHIER_PIN_DRV_STR_MASK ((1UL << (UNIPHIER_PIN_DRV_STR_BITS)) \ +#define UNIPHIER_PIN_DRV_TYPE_BITS 3 +#define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \ - 1) /* pull-up / pull-down register number */ -#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_STR_SHIFT) + \ - (UNIPHIER_PIN_DRV_STR_BITS)) +#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \ + (UNIPHIER_PIN_DRV_TYPE_BITS)) #define UNIPHIER_PIN_PUPDCTRL_BITS 9 #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\ - 1) @@ -68,13 +68,13 @@ struct platform_device; #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK) -/* selectable drive strength */ -enum uniphier_pin_drv_str { - UNIPHIER_PIN_DRV_4_8, /* 2 level control: 4/8 mA */ - UNIPHIER_PIN_DRV_8_12_16_20, /* 4 level control: 8/12/16/20 mA */ - UNIPHIER_PIN_DRV_FIXED_4, /* fixed to 4mA */ - UNIPHIER_PIN_DRV_FIXED_5, /* fixed to 5mA */ - UNIPHIER_PIN_DRV_FIXED_8, /* fixed to 8mA */ +/* drive control type */ +enum uniphier_pin_drv_type { + UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */ + UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */ + UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */ + UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */ + UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */ UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */ }; @@ -91,17 +91,17 @@ enum uniphier_pin_pull_dir { (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT)) #define UNIPHIER_PIN_DRVCTRL(x) \ (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT)) -#define UNIPHIER_PIN_DRV_STR(x) \ - (((x) & (UNIPHIER_PIN_DRV_STR_MASK)) << (UNIPHIER_PIN_DRV_STR_SHIFT)) +#define UNIPHIER_PIN_DRV_TYPE(x) \ + (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT)) #define UNIPHIER_PIN_PUPDCTRL(x) \ (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT)) #define UNIPHIER_PIN_PULL_DIR(x) \ (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT)) -#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_str, pupdctrl, pull_dir)\ +#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\ (UNIPHIER_PIN_IECTRL(iectrl) | \ UNIPHIER_PIN_DRVCTRL(drvctrl) | \ - UNIPHIER_PIN_DRV_STR(drv_str) | \ + UNIPHIER_PIN_DRV_TYPE(drv_type) | \ UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \ UNIPHIER_PIN_PULL_DIR(pull_dir)) @@ -117,10 +117,10 @@ static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data) UNIPHIER_PIN_DRVCTRL_MASK; } -static inline unsigned int uniphier_pin_get_drv_str(void *drv_data) +static inline unsigned int uniphier_pin_get_drv_type(void *drv_data) { - return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_STR_SHIFT) & - UNIPHIER_PIN_DRV_STR_MASK; + return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) & + UNIPHIER_PIN_DRV_TYPE_MASK; } static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data) |