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authorThierry Reding <treding@nvidia.com>2020-03-19 15:27:37 +0300
committerLinus Walleij <linus.walleij@linaro.org>2020-03-27 13:46:06 +0300
commit368b62f2fd077d4c7db09461e8e24f07491a513d (patch)
treef41a2b2b9bd20bbbf2eb9d8149b06a8b4d3169d0 /drivers/pinctrl/tegra/pinctrl-tegra.h
parent103afc8e9e8c4eff96052b311d19f7c32b653ebb (diff)
downloadlinux-368b62f2fd077d4c7db09461e8e24f07491a513d.tar.xz
pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part of the GPIO controller's register programming. Starting with Tegra186, a pin is configured as GPIO or SFIO with a bit in a configuration register of the pin controller. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/tegra/pinctrl-tegra.h')
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 520865979d4a..fcad7f74c5a2 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -107,6 +107,7 @@ struct tegra_function {
* drvup, slwr, slwf, and drvtype parameters.
* @drv_bank: Drive fields register bank.
* @hsm_bit: High Speed Mode register bit.
+ * @sfsel_bit: GPIO/SFIO selection register bit.
* @schmitt_bit: Schmitt register bit.
* @lpmd_bit: Low Power Mode register bit.
* @drvdn_bit: Drive Down register bit.
@@ -153,6 +154,7 @@ struct tegra_pingroup {
s32 ioreset_bit:6;
s32 rcv_sel_bit:6;
s32 hsm_bit:6;
+ s32 sfsel_bit:6;
s32 schmitt_bit:6;
s32 lpmd_bit:6;
s32 drvdn_bit:6;
@@ -192,6 +194,7 @@ struct tegra_pinctrl_soc_data {
bool hsm_in_mux;
bool schmitt_in_mux;
bool drvtype_in_mux;
+ bool sfsel_in_mux;
};
extern const struct dev_pm_ops tegra_pinctrl_pm;