diff options
| author | Ondrej Jirman <megous@megous.com> | 2019-04-13 19:54:13 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-04-23 13:31:42 +0300 |
| commit | cc62383fcebe7f03c274462790fd912f4346304b (patch) | |
| tree | 4c240ae16567212ec6d50baac257bba55c0e5da7 /drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | |
| parent | f7275345728a0ff18a0607dd3706f2ca25dc53e0 (diff) | |
| download | linux-cc62383fcebe7f03c274462790fd912f4346304b.tar.xz | |
pinctrl: sunxi: Support I/O bias voltage setting on H6
H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.
Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).
This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:
commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c')
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index ef4268cc6227..3cc1121589c9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { .irq_banks = 4, .irq_bank_map = h6_irq_bank_map, .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int h6_pinctrl_probe(struct platform_device *pdev) |